1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_COMMON_BLOCK_FAST_SPI 4 bool 5 select SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS 6 help 7 Intel Processor common FAST_SPI support 8 9config FAST_SPI_DISABLE_WRITE_STATUS 10 bool "Disable write status SPI opcode" 11 depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI 12 default n if CHROMEOS 13 default y 14 help 15 Disable the write status SPI opcode in Intel Fast SPI block. 16 17config FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW 18 bool 19 depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI 20 # Enable X86_CUSTOM_BOOTMEDIA because the fast SPI controller 21 # driver provides a custom boot media device when multiple decode 22 # windows are used for the BIOS region. 23 select X86_CUSTOM_BOOTMEDIA 24 help 25 Fast SPI controller on the platform supports additional 26 window for memory mapping BIOS region (region 1) on the SPI 27 flash beyond the standard limit of 16MiB. Depending upon the 28 size of the SPI flash part used by the mainboard, two decode 29 windows will be enabled: 30 1. Fixed decode window up to a maximum size of 16MiB under 31 4G boundary. 32 2. Extended decode window up to a maximum size provided by 33 the platform to map the rest of the BIOS region. 34 SoC selecting this config is expected to provide the base and 35 maximum size of the extended window in the host address space 36 using configs EXT_BIOS_WIN_BASE and EXT_BIOS_WIN_SIZE. 37 38config EXT_BIOS_WIN_BASE 39 hex 40 help 41 If an additional window for mapping BIOS region greater than 42 16MiB is supported, then this config is used to provide the 43 base address reserved for the mapping. Since the mapping is 44 done at the top of the window, depending upon the size of the 45 BIOS region, the actual base address configured in the fast 46 SPI controller can be higher at runtime. 47 48config EXT_BIOS_WIN_SIZE 49 hex 50 help 51 Maximum size of the extended window reserved for mapping BIOS 52 region greater than 16MiB. The actual mapped window might be 53 smaller depending upon the size of the BIOS region. 54 55config FAST_SPI_GENERATE_SSDT 56 bool 57 default n 58 help 59 Select this option if the Fast SPI controller is hidden from the OS. 60 If this switch is selected, an entry in the SSDT will be generated 61 for the controller to report the occupied resource which is not 62 discoverable at OS runtime. 63