1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_COMMON_BLOCK_CPU 4 bool 5 default n 6 help 7 This option selects Intel Common CPU Model support code 8 which provides various CPU related APIs which are common 9 between all Intel Processor families. Common CPU code is supported 10 for SOCs starting from SKL,KBL,APL, and future. 11 12config SOC_INTEL_COMMON_BLOCK_CPU_MPINIT 13 bool 14 default n 15 help 16 This option selects Intel Common CPU MP Init code. In 17 this common MP Init mechanism, the MP Init is occurring before 18 calling FSP Silicon Init. Hence, MP Init will be pulled to 19 BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is 20 ensured that all MTRRs are re-programmed based on the DRAM 21 resource settings. 22 23choice 24 prompt "Application Processors (AP) Feature Programming Configuration to use" 25 default USE_FSP_FEATURE_PROGRAM_ON_APS if MP_SERVICES_PPI_V1 || MP_SERVICES_PPI_V2 26 default USE_COREBOOT_MP_INIT if MP_SERVICES_PPI_V2_NOOP 27 28config USE_FSP_FEATURE_PROGRAM_ON_APS 29 bool "Allow FSP running CPU feature programming on MP init" 30 help 31 Upon selection, coreboot brings APs from reset and the FSP runs feature programming. 32 33config USE_COREBOOT_MP_INIT 34 bool "Use coreboot MP init" 35 # FSP assumes ownership of the APs (Application Processors) 36 # upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. 37 # Hence, select `MP_SERVICES_PPI_V2_NOOP` config to pass a valid 38 # pointer to the CpuMpPpi UPD with FSP_UNSUPPORTED type APIs. 39 # This will protect APs from getting hijacked by FSP while coreboot 40 # decides to set SkipMpInit UPD. 41 select RELOAD_MICROCODE_PATCH 42 help 43 Upon selection, coreboot performs MP Init. 44 45endchoice 46 47config SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE 48 bool 49 depends on SOC_INTEL_COMMON_BLOCK_CPU 50 51config SOC_INTEL_COMMON_BLOCK_CAR 52 bool 53 default n 54 help 55 This option allows you to select how cache-as-ram (CAR) is set up. 56 57config INTEL_CAR_NEM 58 bool 59 default n 60 help 61 Traditionally, CAR is set up by using Non-Evict mode. This method 62 does not allow CAR and cache to co-exist, because cache fills are 63 blocked in NEM. 64 65config INTEL_CAR_CQOS 66 bool 67 default n 68 help 69 Cache Quality of Service allows more fine-grained control of cache 70 usage. As result, it is possible to set up a portion of L2 cache for 71 CAR and use the remainder for actual caching. 72 73config INTEL_CAR_NEM_ENHANCED 74 bool 75 default n 76 help 77 A current limitation of NEM (Non-Evict mode) is that code and data sizes 78 are derived from the requirement to not write out any modified cache line. 79 With NEM, if there is no physical memory behind the cached area, 80 the modified data will be lost and NEM results will be inconsistent. 81 ENHANCED NEM guarantees that modified data is always 82 kept in cache while clean data is replaced. 83 84config CAR_HAS_SF_MASKS 85 bool 86 depends on INTEL_CAR_NEM_ENHANCED 87 help 88 In the case of non-inclusive cache architecture Snoop Filter MSR 89 IA32_L3_SF_MASK_x programming is required along with the data ways. 90 This is applicable for TGL and beyond. 91 92config SF_MASK_2WAYS_PER_BIT 93 bool 94 depends on INTEL_CAR_NEM_ENHANCED 95 help 96 In the case of non-inclusive cache architecture when two ways in 97 the SF mask are controlled by one bit of the SF QoS register. 98 This is applicable for TGL alone. 99 100config COS_MAPPED_TO_MSB 101 bool 102 depends on INTEL_CAR_NEM_ENHANCED 103 help 104 On TGL and JSL platform the class of service configuration 105 is mapped to MSB of MSR IA32_PQR_ASSOC. 106 107config CAR_HAS_L3_PROTECTED_WAYS 108 bool 109 depends on INTEL_CAR_NEM_ENHANCED 110 help 111 On ADL and onwards platform has a newer requirement to protect 112 L3 ways in Non-Inclusive eNEM mode. Hence, MSR 0xc85 is to program 113 the data ways. 114 115config USE_INTEL_FSP_MP_INIT 116 bool "Perform MP Initialization by FSP" 117 default n 118 depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI 119 help 120 This option allows FSP to perform multiprocessor initialization. 121 122config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI 123 bool "Perform MP Initialization by FSP using coreboot MP PPI service" 124 default y 125 depends on MP_SERVICES_PPI 126 help 127 This option allows FSP to make use of MP services PPI published by 128 coreboot to perform multiprocessor initialization. 129 130config CPU_SUPPORTS_INTEL_TME 131 bool 132 default n 133 help 134 Select this if the SoC supports Intel Total Memory Encryption (TME). 135 136config INTEL_TME 137 bool "Total Memory Encryption (TME)/Multi-key TME (MKTME)" 138 depends on CPU_SUPPORTS_INTEL_TME 139 default y 140 help 141 Enable Total Memory Encryption (TME)/Multi-key TME (MKTME). The spec is 142 available at "https://software.intel.com/sites/default/files/managed/a5 143 /16/Multi-Key-Total-Memory-Encryption-Spec.pdf". If CPU supports TME, 144 it would get enabled. If CPU supports MKTME, this same config option 145 enables MKTME. 146 147config TME_KEY_REGENERATION_ON_WARM_BOOT 148 bool "Generate new TME key on each warm boot" 149 depends on INTEL_TME 150 default n 151 help 152 Program Intel TME to generate a new key for each warm boot. TME always 153 generates a new key on each cold boot. With this option enabled TME 154 generates a new key even in warm boot. Without this option TME reuses 155 the key for warm boot. 156 157 If a new key is generated on warm boot, DRAM contents from previous 158 warm boot will not get decrypted. This creates issue in accessing 159 CBMEM region from previous warm boot. To mitigate the issue coreboot 160 also programs exclusion range. Intel TME does not encrypt physical 161 memory range set in exclusion range. Current coreboot implementation 162 programs TME to exclude CBMEM region. When this config option is 163 enabled, coreboot instructs Intel FSP to program TME to generate 164 a new key on every warm boot and also exclude CBMEM region from being 165 encrypted by TME. 166 167config CPU_XTAL_HZ 168 int 169 help 170 Base clock which virtually everything runs on. 171 172config CPU_SUPPORTS_PM_TIMER_EMULATION 173 bool 174 default n 175 help 176 Select this if the SoC's ucode supports PM ACPI timer emulation (Common 177 timer Copy), which is required to be able to disable the TCO PM ACPI 178 timer for power saving. 179 180config SOC_INTEL_NO_BOOTGUARD_MSR 181 bool 182 help 183 Select this on platforms that do not support Bootguard related MSRs 184 0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO. 185 186config SOC_INTEL_DISABLE_POWER_LIMITS 187 bool 188 default n 189 help 190 Select this if the Running Average Power Limits (RAPL) algorithm 191 for constant power management is not needed. 192 193config SOC_INTEL_SET_MIN_CLOCK_RATIO 194 bool 195 depends on !SOC_INTEL_DISABLE_POWER_LIMITS 196 default n 197 help 198 If the power budget of the mainboard is limited, it can be useful to 199 limit the CPU power dissipation at the cost of performance by setting 200 the lowest possible CPU clock. Enable this option if you need smallest 201 possible CPU clock. This setting can be overruled by the OS if it has an 202 p-state driver which can adjust the clock to its need. 203 204config HAVE_HYPERTHREADING 205 def_bool n 206 207config FSP_HYPERTHREADING 208 bool "Enable Hyper-Threading" 209 depends on HAVE_HYPERTHREADING 210 default y 211 212config INTEL_KEYLOCKER 213 bool "Intel Key Locker" 214 default n 215 help 216 Enable Intel Key Locker if supported by the CPU. Intel Key Locker provides a 217 mechanism to encrypt and decrypt data with an AES key without having access 218 to the raw key value by converting AES keys into "handles". The specification 219 of Key Locker can be found via document #343965 on Intel's site. 220 221config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE 222 int 223 depends on INTEL_KEYLOCKER || SOC_INTEL_COMMON_BLOCK_SGX_ENABLE 224 default 256 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB || SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX 225 default 128 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB 226 default 64 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB 227 default 32 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB 228 default 16 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB 229 default 8 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB 230 default 4 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB 231 default 2 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB 232 default 0 if SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB 233 default 0 234 235choice 236 prompt "PRMRR size" 237 depends on INTEL_KEYLOCKER || SOC_INTEL_COMMON_BLOCK_SGX 238 default SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX if SOC_INTEL_COMMON_BLOCK_SGX_ENABLE 239 default SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE && INTEL_KEYLOCKER 240 default SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB if !SOC_INTEL_COMMON_BLOCK_SGX_ENABLE && !INTEL_KEYLOCKER 241 help 242 PRMRR (Protected Memory Range) is the space in RAM that is used to provide a 243 protected memory area (e.g. for the Intel SGX Secure Enclaves and Intel 244 Key Locker). The memory region is accessible only by the processor itself to 245 protect the data from unauthorized access. 246 247 This option allows to select PRMRR size for the intended feature. Depending on 248 the SoC a lower, compatible value may be chosen at runtime as not all values 249 are supported on all families. 250 251config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX 252 bool "Maximum" 253 254config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB 255 bool "256 MiB" 256 257config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB 258 bool "128 MiB" 259 260config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB 261 bool "64 MiB" 262 263config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB 264 bool "32 MiB" 265 266config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB 267 bool "16 MiB" 268 269config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB 270 bool "8 MiB" 271 272config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB 273 bool "4 MiB" 274 275config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB 276 bool "2 MiB" 277 278config SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB 279 bool "0 MiB" 280 281endchoice 282