xref: /aosp_15_r20/external/coreboot/src/soc/intel/common/block/acpi/Kconfig (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1## SPDX-License-Identifier: GPL-2.0-only
2
3config SOC_INTEL_COMMON_BLOCK_ACPI
4	depends on SOC_INTEL_COMMON_BLOCK_CPU
5	depends on SOC_INTEL_COMMON_BLOCK_PMC
6	select ACPI_COMMON_MADT_IOAPIC
7	select ACPI_COMMON_MADT_LAPIC if !SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
8	select ACPI_CUSTOM_MADT
9	bool
10	help
11	  Intel Processor common code for ACPI
12
13config SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
14	bool
15
16config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
17	bool
18	depends on HAVE_ACPI_TABLES
19	select ACPI_LPIT
20	help
21	  Generate LPIT table with LPI state entries
22
23config SOC_INTEL_COMMON_BLOCK_ACPI_PEP
24	bool
25	depends on HAVE_ACPI_TABLES
26	help
27	  Generate an Intel Power Engine device object in the SSDT. This is
28	  usually used for providing ACPI hooks for S0ix exit/entry.
29
30config SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
31	bool
32	depends on SOC_INTEL_COMMON_BLOCK_ACPI_PEP
33	help
34	  Generate a 2nd set of _DSM functions for the Power Engine device that
35	  will return a buffer that contains the contents of the PMC's LPM
36	  requirements registers. A kernel can use this to display the
37	  requirements for different LPM substates.
38
39config SOC_INTEL_COMMON_BLOCK_CRASHLOG
40	bool
41	depends on SOC_INTEL_CRASHLOG
42	help
43	  Generate crash data for BERT table
44
45if SOC_INTEL_COMMON_BLOCK_ACPI
46
47config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
48	bool
49	help
50	  Generate CPPC entries for Intel SpeedShift
51
52config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
53	bool
54	help
55	  Defines hybrid CPU specific ACPI helper functions.
56
57config SOC_INTEL_UFS_OCP_TIMER_DISABLE
58	bool
59	help
60	  OCP Timer need to be disabled in SCS UFS IOSF Bridge to
61	  work around the Silicon Issue due to which LTR mechanism
62	  doesn't work.
63
64config SOC_INTEL_UFS_LTR_DISQUALIFY
65	bool
66	help
67	  LTR needs to be disqualified for UFS in D3 to ensure PMC
68	  ignores LTR from UFS IP which is infinite.
69endif
70
71if SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
72
73config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ
74	hex
75	help
76	  Define the slp_s0_residency frequency to be reported in the
77	  LPIT ACPI table.
78
79endif
80