1## SPDX-License-Identifier: GPL-2.0-only 2 3config INTEL_HAS_TOP_SWAP 4 bool 5 help 6 Set this config if the Intel SoC supports top swap feature 7 8if INTEL_HAS_TOP_SWAP 9 10config INTEL_ADD_TOP_SWAP_BOOTBLOCK 11 bool "Include a Top swap bootblock" 12 default n 13 help 14 Intel PCH/Southbridges have feature that it is possible to have 15 the southbridge/PCH look for the bootblock at a 64K or 16 128K/256K/512K/1MB (in case of newer SoCs) offset 17 instead of the usual top of flash. 18 Select this to put a 'second' bootblock. 19 20config INTEL_TOP_SWAP_BOOTBLOCK_SIZE 21 hex "Size of top swap boot block" 22 depends on INTEL_ADD_TOP_SWAP_BOOTBLOCK 23 default 0x10000 24 help 25 Set this config to a supported topswap size. 26 Valid sizes: 0x10000 0x20000 0x40000 0x80000 0x100000 27 28config INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG 29 string 30 depends on INTEL_ADD_TOP_SWAP_BOOTBLOCK 31 help 32 Use this config to specify the name of a FMAP region (which should 33 hold a microcode) whose address as the first entry in the topswap FIT. 34 This is useful in creating a asymmetric FIT in top swap bootblock 35 than the one in non-topswap bootblock. This string will be passed 36 onto ifittool (-A -n option). ifittool will not parse the region for MCU 37 entries, and only locate the region and insert its address into FIT. 38 39endif 40 41config SOC_INTEL_COMMON 42 bool 43 select AZALIA_HDA_CODEC_SUPPORT 44 select ACPI_SOC_NVS 45 help 46 common code for Intel SOCs 47 48if SOC_INTEL_COMMON 49 50comment "Intel SoC Common Code for IP blocks" 51source "src/soc/intel/common/block/Kconfig" 52 53comment "Intel SoC Common PCH Code" 54source "src/soc/intel/common/pch/Kconfig" 55 56comment "Intel SoC Common coreboot stages and non-IP blocks" 57source "src/soc/intel/common/basecode/Kconfig" 58 59config SOC_INTEL_COMMON_RESET 60 bool 61 default n 62 select HAVE_CF9_RESET 63 64config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE 65 bool 66 default n 67 68config ACPI_CONSOLE 69 bool 70 default n 71 help 72 Provide a mechanism for serial console based ACPI debug. 73 74config PAVP 75 bool "Enable PAVP (Protected Audio-Video Path) support" 76 default y 77 help 78 Protected Audio-Video Path is an Intel technology used to enforce digital 79 rights protections on multimedia content. Streaming or other media playback 80 services may require it to be enabled for correct functioning. 81 82 Users might disable PAVP if the concept of digital rights management (DRM) 83 offends them, or if they have concerns about the security of 84 the Management Engine, which is where this technology is implemented. 85 86 Set this option to n to disable support. 87 88config MMA 89 bool "Enable MMA (Memory Margin Analysis) support for Intel Core" 90 default n 91 depends on SOC_INTEL_KABYLAKE || SOC_INTEL_SKYLAKE 92 help 93 Set this option to y to enable MMA (Memory Margin Analysis) support 94 95config MMA_BLOBS_PATH 96 string "Path to MMA blobs" 97 depends on MMA 98 default "3rdparty/blobs/soc/intel/kabylake/mma-blobs" if SOC_INTEL_KABYLAKE 99 default "3rdparty/blobs/soc/intel/skylake/mma-blobs" if SOC_INTEL_SKYLAKE 100 101config SOC_INTEL_COMMON_NHLT 102 bool 103 default n 104 105config TPM_TIS_ACPI_INTERRUPT 106 int 107 help 108 acpi_get_gpe() is used to provide interrupt status to TPM layer. 109 This option specifies the GPE number. 110 111config SOC_INTEL_DEBUG_CONSENT 112 bool "Enable SOC debug interface" 113 default n 114 help 115 Set this option to enable default debug interface of SoC such as DBC 116 or DCI. 117 118config HAVE_INTEL_COMPLIANCE_TEST_MODE 119 def_bool n 120 121config SOC_INTEL_COMPLIANCE_TEST_MODE 122 bool "Enable SoC hardware compliance test mode" 123 depends on HAVE_INTEL_COMPLIANCE_TEST_MODE 124 default n 125 help 126 Set this option to configure hardware components in a way 127 that supports compliance testing activities for various 128 components such PCIe or USB. For example, PCI express 129 implementation must comply with the hardware PCIe 130 specification requirements: Electrical, Configuration, Link 131 Protocol and Transaction Protocol. The hardware must be 132 configured in a particular state to run the compliance 133 tests: some feature related to power management needs to be 134 turned off, hot plug should be enabled... 135 136config SMM_MODULE_STACK_SIZE 137 hex 138 default 0x800 139 140config SOC_INTEL_CRASHLOG 141 def_bool n 142 select SOC_INTEL_COMMON_BLOCK_CRASHLOG 143 select ACPI_BERT 144 help 145 Enables Crashlog. 146 147config SOC_INTEL_CRASHLOG_ON_RESET 148 def_bool n 149 help 150 Enables the PMC to collect crashlog records on every reset event. NOTE: 151 This will result in a BERT table being populated containing a PMC 152 crashlog record on every boot. 153 154config SOC_INTEL_IOE_DIE_SUPPORT 155 def_bool n 156 help 157 Enable this config if the SOC support IOE DIE. 158 159endif # SOC_INTEL_COMMON 160