1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_EXAMPLE_MIN86 4 bool 5 select ARCH_X86 6 select NO_MONOTONIC_TIMER 7 select NO_ECAM_MMCONF_SUPPORT 8 select UNKNOWN_TSC_RATE 9 help 10 This example SoC code along with the example/min86 mainboard 11 should serve as a minimal example how a buildable x86 SoC code 12 base can look like. 13 14 This can serve, for instance, as a basis to add new SoCs to 15 coreboot. Starting with a buildable commit should help with 16 the review of the actual code, and also avoid any regressions 17 when common coreboot code changes. 18 19if SOC_EXAMPLE_MIN86 20 21config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld 22 default 0x100 23 24endif 25