1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_AMD_COMMON_BLOCK_CAR 4 bool 5 help 6 This option allows the SOC to use a standard AMD cache-as-ram (CAR) 7 implementation. CAR setup is built into bootblock and teardown is 8 in postcar. The teardown procedure does not preserve the stack so 9 it may not be appropriate for a romstage implementation without 10 additional consideration. If this option is not used, the SOC must 11 implement these functions separately. 12 This is only used for AMD CPU before family 17h. From family 17h on 13 the RAM is already initialized by the PSP before the x86 cores are 14 released from reset. 15 16config SOC_AMD_COMMON_BLOCK_NONCAR 17 bool 18 select RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT 19 help 20 From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any 21 more, since the RAM initialization is already done by the PSP when 22 the x86 cores are released from reset. 23 24if SOC_AMD_COMMON_BLOCK_NONCAR 25 26config BOOTBLOCK_IN_CBFS 27 bool 28 default n 29 30config MEMLAYOUT_LD_FILE 31 string 32 default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" 33 34config CBFS_CACHE_SIZE 35 hex 36 help 37 The size of the cbfs_cache region. 38 39config ACPI_CPU_STRING 40 string 41 default "C%03X" 42 43config SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP 44 bool 45 help 46 Disable the legacy DMA decodes again after the call into the 47 reference code in romstage to fix up things. 48 49endif # SOC_AMD_COMMON_BLOCK_NONCAR 50 51config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H 52 bool 53 help 54 Select this option to include code to calculate the CPU frequency 55 from the P state MSR values on AMD CPU families 15h and 16h. 56 57config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H 58 bool 59 help 60 Select this option to include code to calculate the CPU frequency 61 from the P state MSR values on AMD CPU families 17h and 19h. 62 63config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH 64 bool 65 help 66 Select this option to include code to calculate the CPU frequency 67 from the P state MSR values on AMD CPU family 1Ah. 68 69config SOC_AMD_COMMON_BLOCK_MCA_COMMON 70 bool 71 help 72 Add common machine check architecture support. Do not select this 73 in the SoC's Kconfig; select either SOC_AMD_COMMON_BLOCK_MCA or 74 SOC_AMD_COMMON_BLOCK_MCAX which will select this one. 75 76config SOC_AMD_COMMON_BLOCK_MCA 77 bool 78 select SOC_AMD_COMMON_BLOCK_MCA_COMMON 79 help 80 Add IA32 machine check architecture (MCA) support for pre-Zen CPUs. 81 82config SOC_AMD_COMMON_BLOCK_MCAX 83 bool 84 select SOC_AMD_COMMON_BLOCK_MCA_COMMON 85 help 86 Add extended machine check architecture (MCAX) support for AMD family 87 17h, 19h and possibly newer CPUs. 88 89config SOC_AMD_COMMON_BLOCK_SMM 90 bool 91 select X86_SMM_SKIP_RELOCATION_HANDLER if HAVE_SMI_HANDLER 92 help 93 Add common SMM relocation, finalization and handler functionality to 94 the build. 95 96config SOC_AMD_COMMON_LATE_SMM_LOCKING 97 bool 98 depends on SOC_AMD_COMMON_BLOCK_SMM 99 help 100 Select this option to perform SMM locking late in soc_finalize(), rather than earlier 101 in smm_relocation_handler(). This is required for pre-Zen SoCs like Stoneyridge which 102 call into an AGESA binary as part of S3 resume, and require SMM to still be unlocked 103 at that time. 104 105config SOC_AMD_COMMON_BLOCK_SVI2 106 bool 107 help 108 Select this option is the SoC uses the serial VID 2 standard for 109 encoding the voltage it requests from the VRM. 110 111config SOC_AMD_COMMON_BLOCK_SVI3 112 bool 113 help 114 Select this option is the SoC uses the serial VID 3 standard for 115 encoding the voltage it requests from the VRM. 116 117config SOC_AMD_COMMON_BLOCK_TSC 118 bool 119 select TSC_SYNC_LFENCE 120 select UDELAY_TSC 121 select TSC_MONOTONIC_TIMER 122 help 123 Select this option to add the common functions for getting the TSC 124 frequency of AMD family 17h, 19h and 1Ah CPUs/APUs and to provide 125 TSC-based monotonic timer functionality to the build. 126 127config SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSR 128 bool 129 help 130 Select this option to have coreboot sync the PSP_ADDR_MSR from 131 the BSP to all APs. 132 133config SOC_AMD_COMMON_BLOCK_UCODE 134 bool 135 help 136 Builds in support for loading uCode. 137