1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_AMD_COMMON_BLOCK_PSP 4 bool 5 help 6 This option builds in the Platform Security Processor initialization 7 functions. Do not select this directly in SoC code, select 8 SOC_AMD_COMMON_BLOCK_PSP_GENx instead. 9 10config SOC_AMD_COMMON_BLOCK_PSP_GEN1 11 bool 12 select SOC_AMD_COMMON_BLOCK_PSP 13 help 14 Used by the PSP in AMD systems before family 17h, e.g. stoneyridge. 15 16config SOC_AMD_COMMON_BLOCK_PSP_GEN2 17 bool 18 select SOC_AMD_COMMON_BLOCK_PSP 19 select SOC_AMD_COMMON_BLOCK_SMN 20 help 21 Used by the PSP in AMD family 17h, 19h and possibly newer CPUs. 22 23config SOC_AMD_PSP_SELECTABLE_SMU_FW 24 bool 25 help 26 Some PSP implementations allow storing SMU firmware into cbfs and 27 calling the PSP to load the blobs at the proper time. 28 29 The soc/<codename> should select this if its PSP supports the feature 30 and each mainboard can choose to select an appropriate fanless or 31 fanned set of blobs. Ask your AMD representative whether your APU 32 is considered fanless. 33 34config SOC_AMD_COMMON_BLOCK_PSP_SPL 35 bool 36 help 37 Select this option in the SoC's Kconfig to include the Security Patch 38 Level (SPL) support code. This code will only send the actual SPL 39 fuse update command to the PSP if the PERFORM_SPL_FUSING option is 40 also selected. 41 42config PERFORM_SPL_FUSING 43 bool "Send SPL fusing command to PSP" 44 default n 45 depends on SOC_AMD_COMMON_BLOCK_PSP_SPL 46 help 47 Send the Security Patch Level (SPL) fusing command to the PSP in 48 order to update the minimum SPL version to be written to the SoC's 49 fuse bits. This will prevent using any embedded firmware components 50 with lower SPL version. 51 52 If unsure, answer 'n' 53 54config SPL_TABLE_FILE 55 string "SPL table file override" 56 depends on SOC_AMD_COMMON_BLOCK_PSP_SPL 57 help 58 Provide a mainboard-specific Security Patch Level (SPL) table file 59 override. The SPL file is required to support PSP FW anti-rollback 60 and needs to be created by AMD. The default SPL file specified in the 61 SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule 62 and applies to all boards that use the SoC without verstage on PSP. 63 In the verstage on PSP case, a different SPL file is specific as an 64 override via this Kconfig option. 65 66config HAVE_SPL_RW_AB_FILE 67 bool "Have a separate mainboard-specific SPL file in RW A/B partitions" 68 default n 69 depends on SOC_AMD_COMMON_BLOCK_PSP_SPL 70 depends on VBOOT_SLOTS_RW_AB 71 help 72 Have separate mainboard-specific Security Patch Level (SPL) table 73 file for the RW A/B FMAP partitions. 74 75config SPL_RW_AB_TABLE_FILE 76 string "Separate SPL table file override for RW A/B partitions" 77 depends on HAVE_SPL_RW_AB_FILE 78 79config PSP_PLATFORM_SECURE_BOOT 80 bool "Platform secure boot enable" 81 depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2 82 default n 83 help 84 Select this config to enable PSP Platform Secure Boot. 85 86 Platform Secure Boot will automatically be fused on boot if the 87 coreboot ROM is properly signed and can not be disabled once fused. 88 Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is 89 only available with NDA customers. 90 91config PSP_INCLUDES_HSP 92 bool 93 depends on SOC_AMD_COMMON_BLOCK_PSP 94 default n 95 help 96 Select this config to indicate SoC includes Hardware Security Processor(HSP). 97 98config AMD_FWM_POSITION_20000_DEFAULT 99 # This is the default if nothing else is selected 100 bool 101 102config AMD_FWM_POSITION_420000_DEFAULT 103 bool 104 105config AMD_FWM_POSITION_820000_DEFAULT 106 bool 107 108config AMD_FWM_POSITION_C20000_DEFAULT 109 bool 110 111config AMD_FWM_POSITION_E20000_DEFAULT 112 bool 113 114config AMD_FWM_POSITION_F20000_DEFAULT 115 bool 116 117config AMD_FWM_POSITION_FA0000_DEFAULT 118 bool 119 120choice 121 prompt "AMD FW position" 122 default AMD_FWM_POSITION_420000 if AMD_FWM_POSITION_420000_DEFAULT 123 default AMD_FWM_POSITION_820000 if AMD_FWM_POSITION_820000_DEFAULT 124 default AMD_FWM_POSITION_C20000 if AMD_FWM_POSITION_C20000_DEFAULT 125 default AMD_FWM_POSITION_E20000 if AMD_FWM_POSITION_E20000_DEFAULT 126 default AMD_FWM_POSITION_F20000 if AMD_FWM_POSITION_F20000_DEFAULT 127 default AMD_FWM_POSITION_FA0000 if AMD_FWM_POSITION_FA0000_DEFAULT 128 default AMD_FWM_POSITION_20000 129 help 130 Set the position on flash offset where the AMD FW needs to be. 131 This position is relative to a 16MB flash window. If the flash 132 size is smaller than 16MB it gets mapped at the top of that window. 133 134config AMD_FWM_POSITION_20000 135 bool "0x20000" 136 137config AMD_FWM_POSITION_420000 138 bool "0x420000" 139 140config AMD_FWM_POSITION_820000 141 bool "0x820000" 142 143config AMD_FWM_POSITION_C20000 144 bool "0xC20000" 145 146config AMD_FWM_POSITION_E20000 147 bool "0xE20000" 148 149config AMD_FWM_POSITION_F20000 150 bool "0xF20000" 151 152config AMD_FWM_POSITION_FA0000 153 bool "0xFA0000" 154 155endchoice 156 157config AMD_FWM_POSITION 158 hex 159 default 0x20000 if AMD_FWM_POSITION_20000 160 default 0x420000 if AMD_FWM_POSITION_420000 161 default 0x820000 if AMD_FWM_POSITION_820000 162 default 0xc20000 if AMD_FWM_POSITION_C20000 163 default 0xe20000 if AMD_FWM_POSITION_E20000 164 default 0xf20000 if AMD_FWM_POSITION_F20000 165 default 0xfa0000 if AMD_FWM_POSITION_FA0000 166 167config USE_AMDFWTOOL 168 bool 169 default y if SOC_AMD_COMMON_BLOCK_PSP 170 help 171 Select this if AMDFWTOOL needs to be built 172