1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_AMD_COMMON_BLOCK_LPC 4 bool 5 help 6 Select this option to use the traditional LPC-ISA bridge at D14F3. 7 8config PROVIDES_ROM_SHARING 9 bool 10 help 11 Select this option if the LPC bridge supports ROM sharing. 12 13config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA 14 bool 15 select X86_CUSTOM_BOOTMEDIA 16 select SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST 17 depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE 18 help 19 Select this option to enable SPI DMA support. 20 21# The LPC SPI DMA controller requires the source and destination to be 64 byte 22# aligned. 23config CBFS_CACHE_ALIGN 24 int 25 default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA 26 27config FSP_ALIGNMENT_FSP_S 28 int 29 default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA 30 31config FSP_ALIGNMENT_FSP_M 32 int 33 default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA 34 35config SOC_AMD_COMMON_BLOCK_HAS_ESPI 36 bool 37 help 38 Select this option if platform supports eSPI using D14F3 configuration 39 registers. 40 41config SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES 42 bool 43 depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI 44 help 45 Select this if the platform supports 16 instead of 4 eSPI IO decode 46 ranges and 5 instead of 4 eSPI MMIO decode ranges. 47 48config SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE 49 bool 50 depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI 51 help 52 Selected by the SoC if it supports the ALERT_ENABLE bit. 53 54config SOC_AMD_COMMON_BLOCK_USE_ESPI 55 bool 56 depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI 57 help 58 Select this option if mainboard uses eSPI instead of LPC (if supported 59 by platform). 60 61config SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN 62 bool 63 depends on SOC_AMD_COMMON_BLOCK_USE_ESPI 64 help 65 SMU will lock up at times if the port80h enable bit is cleared. Select 66 this option to retain the port80 enable bit while clearing other enable 67 bits in the ESPI Decode register. 68