1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_NVIDIA_TEGRA210 4 bool 5 default n 6 select ARCH_BOOTBLOCK_ARMV4 7 select BOOTBLOCK_CUSTOM 8 select ARCH_VERSTAGE_ARMV4 9 select ARCH_ROMSTAGE_ARMV4 10 select ARCH_RAMSTAGE_ARMV8_64 11 select HAVE_UART_SPECIAL 12 select ARM64_USE_ARM_TRUSTED_FIRMWARE 13 select GENERIC_GPIO_LIB 14 15if SOC_NVIDIA_TEGRA210 16 17config MEMLAYOUT_LD_FILE 18 string 19 default "src/soc/nvidia/tegra210/memlayout.ld" 20 21config VBOOT 22 select VBOOT_STARTS_IN_BOOTBLOCK 23 select VBOOT_SEPARATE_VERSTAGE 24 select VBOOT_RETURN_FROM_VERSTAGE 25 select VBOOT_MUST_REQUEST_DISPLAY 26 27config MAINBOARD_DO_DSI_INIT 28 bool "Use dsi graphics interface" 29 depends on MAINBOARD_DO_NATIVE_VGA_INIT 30 default n 31 select HAVE_LINEAR_FRAMEBUFFER 32 help 33 Initialize dsi display 34 35config MAINBOARD_DO_SOR_INIT 36 bool "Use dp graphics interface" 37 depends on MAINBOARD_DO_NATIVE_VGA_INIT 38 default n 39 select HAVE_LINEAR_FRAMEBUFFER 40 help 41 Initialize dp display 42 43choice 44 prompt "Serial Console UART" 45 default CONSOLE_SERIAL_TEGRA210_UARTA 46 depends on CONSOLE_SERIAL 47 48config CONSOLE_SERIAL_TEGRA210_UARTA 49 bool "UARTA" 50 help 51 Serial console on UART A. 52 53config CONSOLE_SERIAL_TEGRA210_UARTB 54 bool "UARTB" 55 help 56 Serial console on UART B. 57 58config CONSOLE_SERIAL_TEGRA210_UARTC 59 bool "UARTC" 60 help 61 Serial console on UART C. 62 63config CONSOLE_SERIAL_TEGRA210_UARTD 64 bool "UARTD" 65 help 66 Serial console on UART D. 67 68config CONSOLE_SERIAL_TEGRA210_UARTE 69 bool "UARTE" 70 help 71 Serial console on UART E. 72 73endchoice 74 75config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS 76 hex 77 depends on CONSOLE_SERIAL 78 default 0x70006000 if CONSOLE_SERIAL_TEGRA210_UARTA 79 default 0x70006040 if CONSOLE_SERIAL_TEGRA210_UARTB 80 default 0x70006200 if CONSOLE_SERIAL_TEGRA210_UARTC 81 default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD 82 default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE 83 help 84 Map the UART names to the respective MMIO addresses. 85 86config BOOTROM_SDRAM_INIT 87 bool "SoC BootROM does SDRAM init with full BCT" 88 default n 89 help 90 Use during Foster LPDDR4 bringup. 91 92config TRUSTZONE_CARVEOUT_SIZE_MB 93 hex "Size of Trust Zone region" 94 default 0x14 95 help 96 Size of Trust Zone area in MiB to reserve in memory map. 97 98config TTB_SIZE_MB 99 hex "Size of TTB" 100 default 0x4 101 help 102 Maximum size of Translation Table Buffer in MiB. 103 104config SEC_COMPONENT_SIZE_MB 105 hex "Size of resident EL3 components" 106 default 0x10 107 help 108 Maximum size of resident EL3 components in MiB including BL31 and 109 Secure OS. 110 111# Default to 700MHz. This value is based on nv bootloader setting. 112config PLLX_KHZ 113 int 114 default 700000 115 116config HAVE_MTC 117 bool "Add external Memory controller Training Code binary" 118 default n 119 depends on USE_BLOBS 120 help 121 Select this option to add emc training firmware 122 123if HAVE_MTC 124 125config MTC_FILE 126 string "tegra mtc firmware filename" 127 default "tegra_mtc.bin" 128 help 129 The filename of the mtc firmware 130 131config MTC_DIRECTORY 132 string "Directory where MTC firmware file is located" 133 default "." 134 help 135 Path to directory where MTC firmware file is located. 136 137config MTC_ADDRESS 138 hex 139 default 0x81000000 140 help 141 The DRAM location where MTC firmware to be loaded in. This location 142 needs to be consistent with the location defined in tegra_mtc.ld 143 144endif # HAVE_MTC 145 146endif # SOC_NVIDIA_TEGRA210 147