1 /* Copyright 2014 The ChromiumOS Authors 2 * Use of this source code is governed by a BSD-style license that can be 3 * found in the LICENSE file. 4 */ 5 6 #ifndef __CROS_EC_CONFIG_CHIP_H 7 #define __CROS_EC_CONFIG_CHIP_H 8 9 #if defined(BOARD) 10 #include "core/cortex-m/config_core.h" 11 #include "hw_regdefs.h" 12 #endif 13 14 /* Describe the RAM layout */ 15 #define CONFIG_RAM_BASE 0x10000 16 #define CONFIG_RAM_SIZE 0x10000 17 18 /* Flash chip specifics */ 19 #define CONFIG_FLASH_BANK_SIZE 0x800 /* protect bank size */ 20 #define CONFIG_FLASH_ERASE_SIZE 0x800 /* erase bank size */ 21 /* This flash can only be written as 4-byte words (aligned properly, too). */ 22 #define CONFIG_FLASH_WRITE_SIZE 4 /* min write size (bytes) */ 23 /* But we have a 32-word buffer for writing multiple adjacent cells */ 24 #define CONFIG_FLASH_WRITE_IDEAL_SIZE 128 /* best write size (bytes) */ 25 /* The flash controller prevents bulk writes that cross row boundaries */ 26 #define CONFIG_FLASH_ROW_SIZE 256 /* row size */ 27 28 /* Describe the flash layout */ 29 #define CONFIG_PROGRAM_MEMORY_BASE 0x40000 30 #define CONFIG_FLASH_SIZE (512 * 1024) 31 #define CONFIG_FLASH_ERASED_VALUE32 (-1U) 32 #define CONFIG_RO_HEAD_ROOM 1024 /* Room for ROM signature. */ 33 #define CONFIG_RW_HEAD_ROOM CONFIG_RO_HEAD_ROOM /* same for RW */ 34 35 /* Memory-mapped internal flash */ 36 #define CONFIG_INTERNAL_STORAGE 37 #define CONFIG_MAPPED_STORAGE 38 39 /* Program is run directly from storage */ 40 #define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE 41 42 /* Interval between HOOK_TICK notifications */ 43 #define HOOK_TICK_INTERVAL_MS 500 44 #define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) 45 46 /* System stack size */ 47 #define CONFIG_STACK_SIZE 1024 48 49 /* Idle task stack size */ 50 #define IDLE_TASK_STACK_SIZE 512 51 52 /* Default task stack size */ 53 #define TASK_STACK_SIZE 488 54 55 /* Larger task stack size, for hook task */ 56 #define LARGER_TASK_STACK_SIZE 640 57 58 /* Magic for gpio.inc */ 59 #define GPIO_PIN(port, index) (port), (1 << (index)) 60 #define GPIO_PIN_MASK(port, mask) (port), (mask) 61 #define PLACEHOLDER_GPIO_BANK 0 62 63 #define PCLK_FREQ (24 * 1000 * 1000) 64 65 /* Number of IRQ vectors on the NVIC */ 66 #define CONFIG_IRQ_COUNT (GC_INTERRUPTS_COUNT - 15) 67 68 /* We'll have some special commands of our own */ 69 #define CONFIG_EXTENSION_COMMAND 0xbaccd00a 70 71 /* Chip needs to do custom pre-init */ 72 #define CONFIG_CHIP_PRE_INIT 73 74 /* 75 * The flash memory is implemented in two halves. The SoC bootrom will look for 76 * the first-stage bootloader at the beginning of each of the two halves and 77 * prefer the newer one if both are valid. In EC terminology the bootloader 78 * would be called the RO firmware, so we actually have two, not one. The 79 * bootloader also looks in each half of the flash for a valid RW firmware, so 80 * we have two possible RW images as well. The RO and RW images are not tightly 81 * coupled, so either RO image can choose to boot either RW image. 82 * 83 * The EC firmware configuration is not (yet?) prepared to handle multiple, 84 * non-contiguous, RO/RW combinations, so there's a bit of hackery to make this 85 * work. 86 * 87 * The following macros try to make this all work. 88 */ 89 90 /* This isn't optional, since the bootrom will always look for both */ 91 #define CHIP_HAS_RO_B 92 93 /* It's easier for us to consider each half as having its own RO and RW */ 94 #define CFG_FLASH_HALF (CONFIG_FLASH_SIZE >> 1) 95 96 /* 97 * We'll reserve some space at the top of each flash half for persistent 98 * storage and other stuff that's not part of the RW image. We don't promise to 99 * use these two areas for the same thing, it's just more convenient to make 100 * them the same size. 101 */ 102 #define CFG_TOP_SIZE 0x3000 103 #define CFG_TOP_A_OFF (CFG_FLASH_HALF - CFG_TOP_SIZE) 104 #define CFG_TOP_B_OFF (CONFIG_FLASH_SIZE - CFG_TOP_SIZE) 105 106 /* The RO images start at the very beginning of each flash half */ 107 #define CONFIG_RO_MEM_OFF 0 108 #define CHIP_RO_B_MEM_OFF CFG_FLASH_HALF 109 110 /* Size reserved for each RO image */ 111 #define CONFIG_RO_SIZE 0x4000 112 113 /* 114 * RW images start right after the reserved-for-RO areas in each half, but only 115 * because that's where the RO images look for them. It's not a HW constraint. 116 */ 117 #define CONFIG_RW_MEM_OFF CONFIG_RO_SIZE 118 #define CONFIG_RW_B_MEM_OFF (CFG_FLASH_HALF + CONFIG_RW_MEM_OFF) 119 120 /* Size reserved for each RW image */ 121 #define CONFIG_RW_SIZE (CFG_FLASH_HALF - CONFIG_RW_MEM_OFF - CFG_TOP_SIZE) 122 123 /* 124 * These are needed in a couple of places, but aren't very meaningful. Because 125 * we have two RO and two RW images, these values don't really match what's 126 * described in the EC Image Geometry Spec at www.chromium.org. 127 */ 128 /* TODO(wfrichar): Make them meaningful or learn to do without */ 129 #define CONFIG_EC_PROTECTED_STORAGE_OFF 0 130 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_FLASH_SIZE 131 #define CONFIG_EC_WRITABLE_STORAGE_OFF 0 132 #define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_FLASH_SIZE 133 #define CONFIG_RO_STORAGE_OFF 0 134 #define CONFIG_RW_STORAGE_OFF 0 135 #define CONFIG_WP_STORAGE_OFF 0 136 #define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE 137 138 /* 139 * Note: early versions of the SoC would let us build and manually sign our own 140 * bootloaders, and the RW images could be self-signed. Production SoCs require 141 * officially-signed binary blobs to use for the RO bootloader(s), and the RW 142 * images that we build must be manually signed. So even though we generate RO 143 * firmware images, they may not be useful. 144 */ 145 #define CONFIG_CUSTOMIZED_RO 146 147 /* Number of I2C ports */ 148 #define I2C_PORT_COUNT 2 149 150 #define CONFIG_FLASH_LOG_SPACE CONFIG_FLASH_BANK_SIZE 151 152 /* 153 * Flash log occupies space in the top of RO_B section, its counterpart in 154 * RO_A is occupied by the certs. 155 */ 156 #define CONFIG_FLASH_LOG_BASE \ 157 (CONFIG_PROGRAM_MEMORY_BASE + CHIP_RO_B_MEM_OFF + CONFIG_RO_SIZE - \ 158 CONFIG_FLASH_LOG_SPACE) 159 160 /* Space reserved for RO hashes */ 161 #define AP_RO_DATA_SPACE_SIZE CONFIG_FLASH_BANK_SIZE 162 #define AP_RO_DATA_SPACE_ADDR (CONFIG_FLASH_LOG_BASE - AP_RO_DATA_SPACE_SIZE) 163 164 /* Maximum space available for the RO image */ 165 #define MAX_RO_CODE_SIZE (CONFIG_RO_SIZE - CONFIG_FLASH_LOG_SPACE - \ 166 AP_RO_DATA_SPACE_SIZE) 167 168 /* Use software crypto (libcryptoc). */ 169 #define CONFIG_LIBCRYPTOC 170 #endif /* __CROS_EC_CONFIG_CHIP_H */ 171