1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_APOLLOLAKE 4 bool 5 select INTEL_CAR_CQOS 6 select ACPI_INTEL_HARDWARE_SLEEP_VALUES 7 select ACPI_NO_PCAT_8259 8 select ARCH_X86 9 select BOOT_DEVICE_SUPPORTS_WRITES 10 # CPU specific options 11 select CPU_INTEL_COMMON 12 select CPU_SUPPORTS_PM_TIMER_EMULATION 13 select PCR_COMMON_IOSF_1_0 14 select SSE2 15 select SUPPORT_CPU_UCODE_IN_CBFS 16 # Audio options 17 select ACPI_NHLT 18 select SOC_INTEL_COMMON_NHLT 19 # Misc options 20 select CACHE_MRC_SETTINGS 21 select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 22 select FAST_SPI_GENERATE_SSDT 23 select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS 24 select FSP_STATUS_GLOBAL_RESET_REQUIRED_5 25 select GENERIC_GPIO_LIB 26 select HAVE_ASAN_IN_ROMSTAGE 27 select HAVE_CF9_RESET_PREPARE 28 select HAVE_DPTF_EISA_HID 29 select HAVE_FSP_GOP 30 select HAVE_FSP_LOGO_SUPPORT 31 select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE 32 select HAVE_SMI_HANDLER 33 select INTEL_DESCRIPTOR_MODE_CAPABLE 34 select INTEL_GMA_ACPI 35 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP 36 select INTEL_GMA_SWSMISCI 37 select MRC_SETTINGS_PROTECT 38 select MRC_SETTINGS_VARIABLE_DATA 39 select NO_PM_ACPI_TIMER 40 select NO_UART_ON_SUPERIO 41 select NO_XIP_EARLY_STAGES 42 select FSP_COMPRESS_FSP_M_LZ4 43 select PARALLEL_MP_AP_WORK 44 select PCIEXP_ASPM 45 select PCIEXP_COMMON_CLOCK 46 select PCIEXP_CLK_PM 47 select PCIEXP_L1_SUB_STATE 48 select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B 49 select PLATFORM_USES_FSP2_0 50 select PMC_INVALID_READ_AFTER_WRITE 51 select PMC_GLOBAL_RESET_ENABLE_LOCK 52 select REG_SCRIPT 53 select SA_ENABLE_IMR 54 select SOC_INTEL_COMMON 55 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE 56 select SOC_INTEL_COMMON_BLOCK 57 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT 58 select SOC_INTEL_COMMON_BLOCK_ACPI 59 select SOC_INTEL_COMMON_BLOCK_CAR 60 select SOC_INTEL_COMMON_BLOCK_CPU 61 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT 62 select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES 63 select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY 64 select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR 65 select SOC_INTEL_COMMON_PCH_CLIENT 66 select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE 67 select SOC_INTEL_COMMON_BLOCK_SRAM 68 select SOC_INTEL_COMMON_BLOCK_SA 69 select SOC_INTEL_COMMON_BLOCK_SCS 70 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG 71 select SOC_INTEL_COMMON_BLOCK_SMM 72 select SOC_INTEL_COMMON_FSP_RESET 73 select SOC_INTEL_COMMON_RESET 74 select SOC_INTEL_INTEGRATED_SOUTHCLUSTER 75 select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION 76 select SOC_INTEL_NO_BOOTGUARD_MSR 77 select TSC_MONOTONIC_TIMER 78 select UDELAY_TSC 79 select UDK_2017_BINDING 80 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 81 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 82 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 83 # This SoC does not map SPI flash like many previous SoC. Therefore we 84 # provide a custom media driver that facilitates mapping 85 select X86_CUSTOM_BOOTMEDIA 86 help 87 Intel Apollolake support 88 89config SOC_INTEL_GEMINILAKE 90 bool 91 default n 92 select SOC_INTEL_APOLLOLAKE 93 select SOC_INTEL_COMMON_BLOCK_CNVI 94 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT 95 select SOC_INTEL_COMMON_BLOCK_SGX 96 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 97 select IDT_IN_EVERY_STAGE 98 select PAGING_IN_CACHE_AS_RAM 99 select INTEL_CAR_NEM 100 help 101 Intel Geminilake support 102 103if SOC_INTEL_APOLLOLAKE 104 105config USE_LEGACY_8254_TIMER 106 default y 107 108config SKIP_CSE_RBP 109 bool 110 default y if BOOT_DEVICE_MEMORY_MAPPED 111 help 112 Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch 113 firmware for us if we are using memory-mapped SPI. This lets CSE 114 state machine transition to next boot state, so that it can function 115 as designed. 116 117config DISABLE_HECI1_AT_PRE_BOOT 118 default y 119 120config MAX_HECI_DEVICES 121 int 122 default 3 123 124config MAX_CPUS 125 int 126 default 4 127 128config VBOOT 129 select VBOOT_SEPARATE_VERSTAGE 130 select VBOOT_MUST_REQUEST_DISPLAY 131 select VBOOT_STARTS_IN_BOOTBLOCK 132 select VBOOT_VBNV_CMOS if !VBOOT_VBNV_FLASH 133 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH if !VBOOT_VBNV_FLASH 134 135config TPM_ON_FAST_SPI 136 bool 137 default n 138 depends on MEMORY_MAPPED_TPM 139 help 140 TPM part is conntected on Fast SPI interface and is mapped to the 141 linear address space. 142 143config PCR_BASE_ADDRESS 144 hex 145 default 0xd0000000 146 help 147 This option allows you to select MMIO Base Address of sideband bus. 148 149config DCACHE_RAM_BASE 150 hex 151 default 0xfef00000 152 153config DCACHE_RAM_SIZE 154 hex 155 default 0x100000 if SOC_INTEL_GEMINILAKE 156 default 0xc0000 157 help 158 The size of the cache-as-ram region required during bootblock 159 and/or romstage. 160 161config DCACHE_BSP_STACK_SIZE 162 hex 163 default 0x4000 164 help 165 The amount of anticipated stack usage in CAR by bootblock and 166 other stages. 167 168config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ 169 int 170 default 100 171 172config CPU_XTAL_HZ 173 default 19200000 174 175config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 176 int 177 default 133 178 179# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. 180config C_ENV_BOOTBLOCK_SIZE 181 hex 182 default 0x8000 183 184config ROMSTAGE_ADDR 185 hex 186 default 0xfef20000 187 help 188 The base address (in CAR) where romstage should be linked 189 190config VERSTAGE_ADDR 191 hex 192 default 0xfef40000 193 help 194 The base address (in CAR) where verstage should be linked 195 196config FSP_HEADER_PATH 197 default "src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.0.0" if VENDOR_GOOGLE && SOC_INTEL_GEMINILAKE 198 default "src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.3.1" if SOC_INTEL_GEMINILAKE 199 default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/" 200 201config FSP_FD_PATH 202 default "3rdparty/fsp/ApolloLakeFspBinPkg/FspBin/Fsp.fd" 203 204config FSP_M_ADDR 205 hex 206 default 0xfef40000 207 help 208 The address FSP-M will be relocated to during build time 209 210config NEED_LBP2 211 bool "Write contents for logical boot partition 2." 212 default n 213 help 214 Write the contents from a file into the logical boot partition 2 215 region defined by LBP2_FMAP_NAME. 216 217config LBP2_FMAP_NAME 218 string "Name of FMAP region to put logical boot partition 2" 219 depends on NEED_LBP2 220 default "SIGN_CSE" 221 help 222 Name of FMAP region to write logical boot partition 2 data. 223 224config LBP2_FROM_IFWI 225 bool "Extract the LBP2 from the IFWI binary" 226 depends on NEED_LBP2 227 default n 228 help 229 The Logical Boot Partition will be automatically extracted 230 from the supplied IFWI binary 231 232config LBP2_FILE_NAME 233 string "Path of file to write to logical boot partition 2 region" 234 depends on NEED_LBP2 && !LBP2_FROM_IFWI 235 default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/lbp2.bin" 236 help 237 Name of file to store in the logical boot partition 2 region. 238 239config NEED_IFWI 240 bool "Write content into IFWI region" 241 default n 242 help 243 Write the content from a file into IFWI region defined by 244 IFWI_FMAP_NAME. 245 246config IFWI_FMAP_NAME 247 string "Name of FMAP region to pull IFWI into" 248 depends on NEED_IFWI 249 default "IFWI" 250 help 251 Name of FMAP region to write IFWI. 252 253config IFWI_FILE_NAME 254 string "Path of file to write to IFWI region" 255 depends on NEED_IFWI 256 default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/ifwi.bin" 257 help 258 Name of file to store in the IFWI region. 259 260config MAX_ROOT_PORTS 261 int 262 default 6 263 264config NHLT_DMIC_1CH_16B 265 bool 266 depends on ACPI_NHLT 267 default n 268 help 269 Include DSP firmware settings for 1 channel 16B DMIC array. 270 271config NHLT_DMIC_2CH_16B 272 bool 273 depends on ACPI_NHLT 274 default n 275 help 276 Include DSP firmware settings for 2 channel 16B DMIC array. 277 278config NHLT_DMIC_4CH_16B 279 bool 280 depends on ACPI_NHLT 281 default n 282 help 283 Include DSP firmware settings for 4 channel 16B DMIC array. 284 285config NHLT_MAX98357 286 bool 287 depends on ACPI_NHLT 288 default n 289 help 290 Include DSP firmware settings for headset codec. 291 292config NHLT_DA7219 293 bool 294 depends on ACPI_NHLT 295 default n 296 help 297 Include DSP firmware settings for headset codec. 298 299config NHLT_RT5682 300 bool 301 depends on ACPI_NHLT 302 default n 303 help 304 Include DSP firmware settings for headset codec. 305# 306# Each bit in QOS mask controls this many bytes. This is calculated as: 307# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS 308# 309 310config CACHE_QOS_SIZE_PER_BIT 311 hex 312 default 0x20000 # 128 KB 313 314config L2_CACHE_SIZE 315 hex 316 default 0x400000 if SOC_INTEL_GEMINILAKE 317 default 0x100000 318 319config SMM_RESERVED_SIZE 320 hex 321 default 0x100000 322 323config CHIPSET_DEVICETREE 324 string 325 default "soc/intel/apollolake/chipset_glk.cb" if SOC_INTEL_GEMINILAKE 326 default "soc/intel/apollolake/chipset_apl.cb" 327 328config IFD_CHIPSET 329 string 330 default "glk" if SOC_INTEL_GEMINILAKE 331 default "aplk" 332 333config CPU_BCLK_MHZ 334 int 335 default 100 336 337config CONSOLE_UART_BASE_ADDRESS 338 hex 339 default 0xcdffc000 340 depends on INTEL_LPSS_UART_FOR_CONSOLE 341 342# M and N divisor values for clock frequency configuration. 343# These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) 344config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL 345 hex 346 default 0x25a 347 348config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL 349 hex 350 default 0x7fff 351 352config SOC_ESPI 353 bool 354 default n 355 help 356 Use eSPI bus instead of LPC 357 358config SOC_INTEL_COMMON_BLOCK_GSPI_MAX 359 int 360 default 3 361 362config SOC_INTEL_I2C_DEV_MAX 363 int 364 default 8 365 366# Don't include the early page tables in RW_A or RW_B cbfs regions 367config RO_REGION_ONLY 368 string 369 default "pdpt pt" 370 371config INTEL_GMA_PANEL_2 372 bool 373 default n 374 375config INTEL_GMA_BCLV_OFFSET 376 default 0xc8358 if INTEL_GMA_PANEL_2 377 default 0xc8258 378 379config INTEL_GMA_BCLV_WIDTH 380 default 32 381 382config INTEL_GMA_BCLM_OFFSET 383 default 0xc8354 if INTEL_GMA_PANEL_2 384 default 0xc8254 385 386config INTEL_GMA_BCLM_WIDTH 387 default 32 388 389config BOOTBLOCK_IN_CBFS 390 bool 391 default n 392 393config HAVE_PAM0_REGISTER 394 bool 395 default n 396 397config DOMAIN_RESOURCE_32BIT_LIMIT 398 default PCR_BASE_ADDRESS 399 400endif 401