1# SPDX-License-Identifier: GPL-2.0-or-later 2 3source "src/soc/intel/xeon_sp/*/Kconfig" 4 5config XEON_SP_IBL 6 bool 7 default n 8 9config XEON_SP_COMMON_BASE 10 bool 11 select ACPI_INTEL_HARDWARE_SLEEP_VALUES 12 select ARCH_X86 13 select BOOT_DEVICE_SUPPORTS_WRITES 14 select CPU_INTEL_COMMON 15 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE 16 select FSP_CAR 17 select FSP_M_XIP 18 select FSP_COMPRESS_FSP_S_LZ4 19 select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS 20 select FSP_T_XIP 21 select HAVE_SMI_HANDLER 22 select INTEL_CAR_NEM # For postcar only now 23 select INTEL_DESCRIPTOR_MODE_CAPABLE 24 select PARALLEL_MP_AP_WORK 25 select PMC_GLOBAL_RESET_ENABLE_LOCK 26 select POSTCAR_STAGE 27 select REG_SCRIPT 28 select SMM_TSEG 29 select SOC_INTEL_COMMON 30 select SOC_INTEL_COMMON_RESET 31 select SOC_INTEL_COMMON_BLOCK 32 select SOC_INTEL_COMMON_BLOCK_ACPI 33 select SOC_INTEL_COMMON_BLOCK_CPU 34 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT 35 select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL 36 select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE 37 select SOC_INTEL_COMMON_BLOCK_SMM 38 select SOC_INTEL_COMMON_BLOCK_TCO 39 select SUPPORT_CPU_UCODE_IN_CBFS 40 select SMM_PCI_RESOURCE_STORE 41 select SOC_INTEL_COMMON_PCH_SERVER if !XEON_SP_IBL 42 select SOC_INTEL_COMMON_IBL_BASE if XEON_SP_IBL 43 select TSC_MONOTONIC_TIMER 44 select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT 45 select UDELAY_TSC 46 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 47 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 48 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 49 50if XEON_SP_COMMON_BASE 51 52config MAX_SOCKET 53 int 54 default 2 55 56config MAX_HECI_DEVICES 57 int 58 default 5 59 60# For 2S config, the number of cpus could be as high as 61# 2 threads * 20 cores * 2 sockets 62config MAX_CPUS 63 int 64 default 80 65 66config INTEL_ACPI_BASE_ADDRESS 67 hex 68 default 0x500 69 help 70 IO Address of ACPI. 71 72config INTEL_PCH_PWRM_BASE_ADDRESS 73 hex 74 default 0xfe000000 75 help 76 PCH PWRM Base address. 77 78config PCR_BASE_ADDRESS 79 hex 80 default 0xfd000000 81 help 82 This option allows you to select MMIO Base Address of sideband bus. 83 84config DCACHE_BSP_STACK_SIZE 85 hex 86 default 0x10000 87 88config ECAM_MMCONF_BASE_ADDRESS 89 default 0x80000000 90 91config ECAM_MMCONF_BUS_NUMBER 92 default 512 if MAX_SOCKET = 4 93 default 256 94 95config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION 96 default y 97 98config HPET_MIN_TICKS 99 hex 100 default 0x80 101 102config SOC_INTEL_XEON_RAS 103 bool 104 select SOC_ACPI_HEST 105 select SOC_RAS_ELOG 106 107config HAVE_IOAT_DOMAINS 108 bool 109 110config SOC_INTEL_HAS_CXL 111 bool 112 113endif ## SOC_INTEL_XEON_SP 114