1# SPDX-License-Identifier: GPL-2.0-only 2 3config SOUTHBRIDGE_AMD_PI_AVALON 4 bool 5 6config SOUTHBRIDGE_AMD_PI_KERN 7 bool 8 9if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_KERN 10 11config SOUTHBRIDGE_SPECIFIC_OPTIONS 12 def_bool y 13 select ACPI_COMMON_MADT_IOAPIC 14 select ACPI_COMMON_MADT_LAPIC 15 select ACPI_CUSTOM_MADT 16 select HAVE_CONFIGURABLE_APMC_SMI_PORT 17 select HAVE_USBDEBUG_OPTIONS 18 select HAVE_CF9_RESET 19 select HAVE_CF9_RESET_PREPARE 20 select SOC_AMD_COMMON 21 select SOC_AMD_COMMON_BLOCK_ACPIMMIO 22 select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM 23 select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS 24 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS 25 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE 26 select SOC_AMD_COMMON_BLOCK_PCI_MMCONF 27 select USE_AMDFWTOOL 28 29config EHCI_BAR 30 hex 31 default 0xfef00000 32 33config HUDSON_XHCI_ENABLE 34 bool "Enable Hudson XHCI Controller" 35 default y 36 help 37 The XHCI controller must be enabled and the XHCI firmware 38 must be added in order to have USB 3.0 support configured 39 by coreboot. The OS will be responsible for enabling the XHCI 40 controller if the XHCI firmware is available but the 41 XHCI controller is not enabled by coreboot. 42 43config HUDSON_XHCI_FWM 44 bool "Add xhci firmware" 45 default y 46 help 47 Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 48 49config HUDSON_IMC_ENABLE 50 bool 51 default n 52 53config HUDSON_IMC_FWM 54 bool "Add IMC firmware" 55 depends on HUDSON_IMC_ENABLE 56 default y 57 help 58 Add Hudson 2/3/4 IMC Firmware to support the onboard fan control 59 60config HUDSON_GEC_FWM 61 bool 62 default n 63 help 64 Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. 65 Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. 66 67config HUDSON_PSP 68 bool 69 default y if CPU_AMD_PI_00730F01 70 71config AMDFW_CONFIG_FILE 72 string "AMD PSP Firmware config file" 73 default "src/southbridge/amd/pi/hudson/fw_avl.cfg" if CPU_AMD_PI_00730F01 74 75config HUDSON_XHCI_FWM_FILE 76 string "XHCI firmware path and filename" 77 default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON 78 default "3rdparty/blobs/southbridge/amd/kern/xhci.bin" if SOUTHBRIDGE_AMD_PI_KERN 79 depends on HUDSON_XHCI_FWM 80 81config HUDSON_IMC_FWM_FILE 82 string "IMC firmware path and filename" 83 default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON 84 default "3rdparty/blobs/southbridge/amd/kern/imc.bin" if SOUTHBRIDGE_AMD_PI_KERN 85 depends on HUDSON_IMC_FWM 86 87config HUDSON_GEC_FWM_FILE 88 string "GEC firmware path and filename" 89 depends on HUDSON_GEC_FWM 90 91config AMD_PUBKEY_FILE 92 depends on HUDSON_PSP 93 string "AMD public Key" 94 default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 95 96config HUDSON_SATA_MODE 97 int "SATA Mode" 98 default 2 99 range 0 6 100 help 101 Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. 102 The default is NATIVE. 103 0: NATIVE mode does not require a ROM. 104 1: RAID mode must have the two ROM files. 105 2: AHCI may work with or without AHCI ROM. It depends on the payload support. 106 For example, seabios does not require the AHCI ROM. 107 3: LEGACY IDE 108 4: IDE to AHCI 109 5: AHCI7804: ROM Required, and AMD driver required in the OS. 110 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. 111 112comment "NATIVE" 113 depends on HUDSON_SATA_MODE = 0 114 115comment "RAID" 116 depends on HUDSON_SATA_MODE = 1 117 118comment "AHCI" 119 depends on HUDSON_SATA_MODE = 2 120 121comment "LEGACY IDE" 122 depends on HUDSON_SATA_MODE = 3 123 124comment "IDE to AHCI" 125 depends on HUDSON_SATA_MODE = 4 126 127comment "AHCI7804" 128 depends on HUDSON_SATA_MODE = 5 129 130comment "IDE to AHCI7804" 131 depends on HUDSON_SATA_MODE = 6 132 133config HUDSON_FADT_LEGACY_DEVICES 134 bool 135 help 136 Select if there are legacy devices on the LPC bus. 137 138config HUDSON_FADT_8042 139 bool 140 help 141 Select if there is an 8042-compatible keyboard controller in the 142 system. 143 144config AMDFW_OUTSIDE_CBFS 145 def_bool n 146 help 147 The AMDFW (PSP) is typically locatable in cbfs. Select this 148 option to manually attach the generated amdfw.rom at an 149 offset of 0x20000 from the bottom of the coreboot ROM image. 150 151config SERIRQ_CONTINUOUS_MODE 152 bool 153 default n 154 help 155 Set this option to y for serial IRQ in continuous mode. 156 Otherwise it is in quiet mode. 157 158config HUDSON_ACPI_IO_BASE 159 hex 160 default 0x800 161 help 162 Base address for the ACPI registers. 163 This value must match the hardcoded value of AGESA. 164 165endif 166