1# SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_AMD_STONEYRIDGE 4 bool 5 select ACPI_SOC_NVS 6 select ARCH_X86 7 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH 8 select COLLECT_TIMESTAMPS_NO_TSC 9 select GENERIC_GPIO_LIB 10 select GENERIC_UDELAY 11 select HAVE_CF9_RESET 12 select HAVE_SMI_HANDLER 13 select HAVE_USBDEBUG_OPTIONS 14 select PARALLEL_MP_AP_WORK 15 select RTC 16 select SOC_AMD_PI 17 select SOC_AMD_COMMON 18 select SOC_AMD_COMMON_BLOCK_ACPI 19 select SOC_AMD_COMMON_BLOCK_ACPI_GPIO 20 select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE 21 select SOC_AMD_COMMON_BLOCK_ACPI_MADT 22 select SOC_AMD_COMMON_BLOCK_ACPIMMIO 23 select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM 24 select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS 25 select SOC_AMD_COMMON_BLOCK_AOAC 26 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS 27 select SOC_AMD_COMMON_BLOCK_CAR 28 select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H 29 select SOC_AMD_COMMON_BLOCK_GRAPHICS 30 select SOC_AMD_COMMON_BLOCK_HDA 31 select SOC_AMD_COMMON_BLOCK_I2C 32 select SOC_AMD_COMMON_BLOCK_IOMMU 33 select SOC_AMD_COMMON_BLOCK_LPC 34 select SOC_AMD_COMMON_BLOCK_MCA 35 select SOC_AMD_COMMON_BLOCK_PCI 36 select SOC_AMD_COMMON_BLOCK_PM 37 select SOC_AMD_COMMON_BLOCK_PSP_GEN1 38 select SOC_AMD_COMMON_BLOCK_SATA 39 select SOC_AMD_COMMON_BLOCK_SMBUS 40 select SOC_AMD_COMMON_BLOCK_SMI 41 select SOC_AMD_COMMON_BLOCK_SMM 42 select SOC_AMD_COMMON_BLOCK_SMN 43 select SOC_AMD_COMMON_BLOCK_SPI 44 select SOC_AMD_COMMON_BLOCK_SVI2 45 select SOC_AMD_COMMON_BLOCK_UART 46 select SOC_AMD_COMMON_LATE_SMM_LOCKING 47 select SSE2 48 select TSC_SYNC_LFENCE 49 select USE_DDR4 50 select X86_AMD_FIXED_MTRRS 51 help 52 AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh. 53 54if SOC_AMD_STONEYRIDGE 55 56config AMD_APU_STONEYRIDGE 57 bool 58 help 59 AMD Stoney Ridge APU 60 61config AMD_APU_PRAIRIEFALCON 62 bool 63 help 64 AMD Embedded Prairie Falcon APU 65 66config AMD_APU_MERLINFALCON 67 bool 68 help 69 AMD Embedded Merlin Falcon APU 70 71config AMD_APU_PKG_FP4 72 bool 73 help 74 AMD FP4 package 75 76config AMD_APU_PKG_FT4 77 bool 78 help 79 AMD FT4 package 80 81config AMD_SOC_PACKAGE 82 string 83 default "FP4" if AMD_APU_PKG_FP4 84 default "FT4" if AMD_APU_PKG_FT4 85 86config CHIPSET_DEVICETREE 87 string 88 default "soc/amd/stoneyridge/chipset_cz.cb" if AMD_APU_MERLINFALCON 89 default "soc/amd/stoneyridge/chipset_st.cb" if AMD_APU_PRAIRIEFALCON 90 default "soc/amd/stoneyridge/chipset_st.cb" if AMD_APU_STONEYRIDGE 91 92config VBOOT 93 select VBOOT_STARTS_IN_BOOTBLOCK 94 select VBOOT_VBNV_CMOS 95 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH 96 97# TODO: Sync these with definitions in PI vendorcode. 98# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. 99# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. 100 101config DCACHE_RAM_BASE 102 hex 103 default 0x30000 104 105config DCACHE_RAM_SIZE 106 hex 107 default 0x10000 108 109config PRERAM_CBFS_CACHE_SIZE 110 default 0x0 111 112config DCACHE_BSP_STACK_SIZE 113 hex 114 default 0x4000 115 help 116 The amount of anticipated stack usage in CAR by bootblock and 117 other stages. 118 119config PRERAM_CBMEM_CONSOLE_SIZE 120 hex 121 default 0x1600 122 help 123 Increase this value if preram cbmem console is getting truncated 124 125config BOTTOMIO_POSITION 126 hex "Bottom of 32-bit IO space" 127 default 0xD0000000 128 help 129 If PCI peripherals with big BARs are connected to the system 130 the bottom of the IO must be decreased to allocate such 131 devices. 132 133 Declare the beginning of the 128MB-aligned MMIO region. This 134 option is useful when PCI peripherals requesting large address 135 ranges are present. 136 137config ECAM_MMCONF_BASE_ADDRESS 138 default 0xF8000000 139 140config ECAM_MMCONF_BUS_NUMBER 141 default 64 142 143# This number must be equal or lower than what's reported in ACPI PCI _CRS 144config DOMAIN_RESOURCE_32BIT_LIMIT 145 default ECAM_MMCONF_BASE_ADDRESS 146 147config VGA_BIOS_ID 148 string 149 default "1002,9870" if AMD_APU_MERLINFALCON 150 default "1002,98e0" 151 help 152 The default VGA BIOS PCI vendor/device ID should be set to the 153 result of the map_oprom_vendev() function in northbridge.c. 154 155config VGA_BIOS_FILE 156 string 157 default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON 158 default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON 159 default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE 160 161config S3_VGA_ROM_RUN 162 bool 163 default n 164 165config EHCI_BAR 166 hex 167 default 0xfef00000 168 169config STONEYRIDGE_XHCI_ENABLE 170 bool "Enable Stoney Ridge XHCI Controller" 171 default y 172 help 173 The XHCI controller must be enabled and the XHCI firmware 174 must be added in order to have USB 3.0 support configured 175 by coreboot. The OS will be responsible for enabling the XHCI 176 controller if the XHCI firmware is available but the 177 XHCI controller is not enabled by coreboot. 178 179config STONEYRIDGE_XHCI_FWM 180 bool "Add xhci firmware" 181 default y 182 help 183 Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0 184 185config STONEYRIDGE_GEC_FWM 186 bool 187 default n 188 help 189 Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. 190 Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. 191 192config STONEYRIDGE_XHCI_FWM_FILE 193 string "XHCI firmware path and filename" 194 default "3rdparty/amd_blobs/stoneyridge/xhci.bin" 195 depends on STONEYRIDGE_XHCI_FWM 196 197config STONEYRIDGE_GEC_FWM_FILE 198 string "GEC firmware path and filename" 199 depends on STONEYRIDGE_GEC_FWM 200 201config AMDFW_CONFIG_FILE 202 string 203 string "AMD PSP Firmware config file" 204 default "src/soc/amd/stoneyridge/fw_cz.cfg" if AMD_APU_MERLINFALCON 205 default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_PRAIRIEFALCON 206 default "src/soc/amd/stoneyridge/fw_st.cfg" if AMD_APU_STONEYRIDGE 207 208config STONEYRIDGE_SATA_MODE 209 int "SATA Mode" 210 default 0 211 range 0 6 212 help 213 Select the mode in which SATA should be driven. 214 The default is NATIVE. 215 0: NATIVE mode does not require a ROM. 216 2: AHCI may work with or without AHCI ROM. It depends on the payload support. 217 For example, seabios does not require the AHCI ROM. 218 3: LEGACY IDE 219 4: IDE to AHCI 220 5: AHCI7804: ROM Required, and AMD driver required in the OS. 221 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. 222 223comment "NATIVE" 224 depends on STONEYRIDGE_SATA_MODE = 0 225 226comment "AHCI" 227 depends on STONEYRIDGE_SATA_MODE = 2 228 229comment "LEGACY IDE" 230 depends on STONEYRIDGE_SATA_MODE = 3 231 232comment "IDE to AHCI" 233 depends on STONEYRIDGE_SATA_MODE = 4 234 235comment "AHCI7804" 236 depends on STONEYRIDGE_SATA_MODE = 5 237 238comment "IDE to AHCI7804" 239 depends on STONEYRIDGE_SATA_MODE = 6 240 241config STONEYRIDGE_LEGACY_FREE 242 bool "System is legacy free" 243 help 244 Select y if there is no keyboard controller in the system. 245 This sets variables in AGESA and ACPI. 246 247config SERIRQ_CONTINUOUS_MODE 248 bool 249 default n 250 help 251 Set this option to y for serial IRQ in continuous mode. 252 Otherwise it is in quiet mode. 253 254config CONSOLE_UART_BASE_ADDRESS 255 depends on CONSOLE_SERIAL 256 hex 257 default 0xfedc6000 258 259config SMM_TSEG_SIZE 260 hex 261 default 0x800000 if HAVE_SMI_HANDLER 262 default 0x0 263 264config SMM_RESERVED_SIZE 265 hex 266 default 0x160000 267 268config SMM_MODULE_STACK_SIZE 269 hex 270 default 0x800 271 272config ACPI_CPU_STRING 273 string 274 default "P%03X" 275 276config ACPI_SSDT_PSD_INDEPENDENT 277 default n 278 279config ACPI_BERT 280 bool "Build ACPI BERT Table" 281 default y 282 depends on HAVE_ACPI_TABLES 283 help 284 Report Machine Check errors identified in POST to the OS in an 285 ACPI Boot Error Record Table. This option reserves an 8MB region 286 for building the error structures. 287 288config USE_PSPSECUREOS 289 bool "Include PSP SecureOS blobs in AMD firmware" 290 default y 291 help 292 Include the PspSecureOs, PspTrustlet and TrustletKey binaries 293 in the amdfw section. 294 295 If unsure, answer 'y' 296 297config SOC_AMD_PSP_SELECTABLE_SMU_FW 298 bool 299 default y if AMD_APU_STONEYRIDGE 300 help 301 Some ST implementations allow storing SMU firmware into cbfs and 302 calling the PSP to load the blobs at the proper time. 303 304 Merlin Falcon does not support it. If you are using 00670F00 SOC, 305 ask your AMD representative if it supports it or not. 306 307config SOC_AMD_SMU_FANLESS 308 bool 309 depends on SOC_AMD_PSP_SELECTABLE_SMU_FW 310 default n if SOC_AMD_SMU_NOTFANLESS 311 default y 312 313config SOC_AMD_SMU_FANNED 314 bool 315 depends on SOC_AMD_PSP_SELECTABLE_SMU_FW 316 default n 317 select SOC_AMD_SMU_NOTFANLESS 318 319config SOC_AMD_SMU_NOTFANLESS # helper symbol - do not use 320 bool 321 depends on SOC_AMD_PSP_SELECTABLE_SMU_FW 322 323config AMDFW_OUTSIDE_CBFS 324 bool "The AMD firmware is outside CBFS" 325 default n 326 help 327 The AMDFW (PSP) is typically locatable in cbfs. Select this 328 option to manually attach the generated amdfw.rom outside of 329 cbfs. The location is selected by the FWM position. 330 331config DIMM_SPD_SIZE 332 default 512 # DDR4 333 334config RO_REGION_ONLY 335 string 336 depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A 337 default "apu/amdfw" 338 339config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 340 int 341 default 133 342 343config DISABLE_KEYBOARD_RESET_PIN 344 bool 345 help 346 Instruct the SoC to not use the state of GPIO_129 as keyboard reset 347 signal. When this pin is used as GPIO and the keyboard reset 348 functionality isn't disabled, configuring it as an output and driving 349 it as 0 will cause a reset. 350 351config ACPI_BERT_SIZE 352 hex 353 default 0x100000 if ACPI_BERT 354 default 0x0 355 help 356 Specify the amount of DRAM reserved for gathering the data used to 357 generate the ACPI table. 358 359endif # SOC_AMD_STONEYRIDGE 360