1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32WBxx_HAL_FLASH_H 22 #define STM32WBxx_HAL_FLASH_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32wbxx_hal_def.h" 30 31 /** @addtogroup STM32WBxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FLASH 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup FLASH_Exported_Types FLASH Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief FLASH Erase structure definition 46 */ 47 typedef struct 48 { 49 uint32_t TypeErase; /*!< Mass erase or page erase. 50 This parameter can be a value of @ref FLASH_TYPE_ERASE */ 51 uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled 52 This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ 53 uint32_t NbPages; /*!< Number of pages to be erased. 54 This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/ 55 } FLASH_EraseInitTypeDef; 56 57 /** 58 * @brief FLASH Option Bytes Program structure definition 59 */ 60 typedef struct 61 { 62 uint32_t OptionType; /*!< Option byte to be configured. 63 This parameter can be a combination of the values of @ref FLASH_OB_TYPE */ 64 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 65 Only one WRP area could be programmed at the same time. 66 This parameter can be value of @ref FLASH_OB_WRP_AREA */ 67 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 68 This parameter must be a value between 0 and (max number of pages - 1) */ 69 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 70 This parameter must be a value between WRPStartOffset and (max number of pages - 1) */ 71 uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). 72 This parameter can be a value of @ref FLASH_OB_READ_PROTECTION */ 73 uint32_t UserType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 74 This parameter can be a combination of @ref FLASH_OB_USER_TYPE */ 75 uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 76 This parameter can be a combination of the values of 77 @ref FLASH_OB_USER_AGC_TRIM, @ref FLASH_OB_USER_BOR_LEVEL 78 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 79 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 80 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 81 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1, 82 @ref FLASH_OB_USER_SRAM2PE, @ref FLASH_OB_USER_SRAM2RST, 83 @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0 */ 84 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). 85 This parameter must be a combination of values of @ref FLASH_OB_PCROP_ZONE 86 and @ref FLASH_OB_PCROP_RDP */ 87 uint32_t PCROP1AStartAddr; /*!< PCROP Zone A Start address (used for OPTIONBYTE_PCROP). It represents first address of start block 88 to protect. Make sure this parameter is multiple of PCROP granularity */ 89 uint32_t PCROP1AEndAddr; /*!< PCROP Zone A End address (used for OPTIONBYTE_PCROP). It represents first address of end block 90 to protect. Make sure this parameter is multiple of PCROP granularity */ 91 uint32_t PCROP1BStartAddr; /*!< PCROP Zone B Start address (used for OPTIONBYTE_PCROP). It represents first address of start block 92 to protect. Make sure this parameter is multiple of PCROP granularity */ 93 uint32_t PCROP1BEndAddr; /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block 94 to protect. Make sure this parameter is multiple of PCROP granularity */ 95 uint32_t SecureFlashStartAddr; /*!< Secure Flash start address (used for OPTIONBYTE_SECURE_MODE). 96 This parameter must be a value between begin and end of Flash bank 97 => Contains the start address of the first 4kB page of the secure Flash area */ 98 uint32_t SecureRAM2aStartAddr; /*!< Secure Backup RAM2a start address (used for OPTIONBYTE_SECURE_MODE). 99 This parameter can be a value of @ref FLASH_SRAM2A_ADDRESS_RANGE */ 100 uint32_t SecureRAM2bStartAddr; /*!< Secure non-Backup RAM2b start address (used for OPTIONBYTE_SECURE_MODE) 101 This parameter can be a value of @ref FLASH_SRAM2B_ADDRESS_RANGE */ 102 uint32_t SecureMode; /*!< Secure mode activated or desactivated. 103 This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */ 104 uint32_t C2BootRegion; /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT). 105 This parameter can be a value of @ref C2_FLASH_OB_BOOT_REGION */ 106 uint32_t C2SecureBootVectAddr; /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT). 107 This parameter contains the CPU2 boot reset start address within 108 the selected memory region. Make sure this parameter is word aligned. */ 109 uint32_t IPCCdataBufAddr; /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR). 110 This parameter contains the IPCC mailbox data buffer start address area in SRAM2. 111 Make sure this parameter is double-word aligned. */ 112 } FLASH_OBProgramInitTypeDef; 113 114 /** 115 * @brief FLASH handle Structure definition 116 */ 117 typedef struct 118 { 119 HAL_LockTypeDef Lock; /* FLASH locking object */ 120 uint32_t ErrorCode; /* FLASH error code */ 121 uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ 122 uint32_t Address; /* Internal variable to save address selected for program in IT context */ 123 uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ 124 uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 125 } FLASH_ProcessTypeDef; 126 127 /** 128 * @} 129 */ 130 131 /* Exported constants --------------------------------------------------------*/ 132 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 133 * @{ 134 */ 135 136 /** @defgroup FLASH_KEYS FLASH Keys 137 * @{ 138 */ 139 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 140 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 141 to unlock the FLASH registers access */ 142 143 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 144 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 145 to allow option bytes operations */ 146 /** 147 * @} 148 */ 149 150 /** @defgroup FLASH_LATENCY FLASH Latency 151 * @{ 152 */ 153 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 154 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 155 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 156 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 157 /** 158 * @} 159 */ 160 161 /** @defgroup FLASH_FLAGS FLASH Flags Definition 162 * @{ 163 */ 164 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ 165 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ 166 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ 167 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ 168 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ 169 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ 170 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ 171 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ 172 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ 173 #define FLASH_FLAG_OPTNV FLASH_SR_OPTNV /*!< FLASH User Option OPTVAL indication */ 174 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ 175 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 176 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 177 #define FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY /*!< FLASH Programming/erase configuration busy */ 178 #define FLASH_FLAG_PESD FLASH_SR_PESD /*!< FLASH Programming/erase operation suspended */ 179 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 180 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 181 182 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 183 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 184 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 185 FLASH_FLAG_OPTVERR) /*!< All SR error flags */ 186 187 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) 188 189 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) 190 191 /** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition 192 * @brief FLASH Interrupt definition 193 * @{ 194 */ 195 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 196 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ 197 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source */ 198 #define FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction Interrupt source */ 199 /** 200 * @} 201 */ 202 203 /** @defgroup FLASH_ERROR FLASH Error 204 * @{ 205 */ 206 #define HAL_FLASH_ERROR_NONE 0x00000000U 207 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 208 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 209 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 210 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 211 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 212 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 213 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR 214 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR 215 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR 216 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR 217 /** 218 * @} 219 */ 220 221 /** @defgroup FLASH_TYPE_ERASE FLASH Erase Type 222 * @{ 223 */ 224 #define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only*/ 225 #define FLASH_TYPEERASE_MASSERASE FLASH_CR_MER /*!< Flash mass erase activation*/ 226 /** 227 * @} 228 */ 229 230 /** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type 231 * @{ 232 */ 233 #define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address.*/ 234 #define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 64 row double-word (64-bit) at a specified address. 235 And another 64 row double-word (64-bit) will be programmed */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type 241 * @{ 242 */ 243 #define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ 244 #define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ 245 #define OPTIONBYTE_USER 0x00000004U /*!< User option byte configuration */ 246 #define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */ 247 #define OPTIONBYTE_IPCC_BUF_ADDR 0x00000010U /*!< IPCC mailbox buffer address configuration */ 248 #define OPTIONBYTE_C2_BOOT_VECT 0x00000100U /*!< CPU2 Secure Boot reset vector */ 249 #define OPTIONBYTE_SECURE_MODE 0x00000200U /*!< Secure mode on activated or not */ 250 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 251 OPTIONBYTE_PCROP | OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | \ 252 OPTIONBYTE_SECURE_MODE) /*!< All option byte configuration */ 253 /** 254 * @} 255 */ 256 257 /** @defgroup FLASH_OB_WRP_AREA FLASH WRP Area 258 * @{ 259 */ 260 #define OB_WRPAREA_BANK1_AREAA 0x00000000U /*!< Flash Area A */ 261 #define OB_WRPAREA_BANK1_AREAB 0x00000001U /*!< Flash Area B */ 262 /** 263 * @} 264 */ 265 266 /** @defgroup FLASH_OB_READ_PROTECTION FLASH Option Bytes Read Protection 267 * @{ 268 */ 269 #define OB_RDP_LEVEL_0 0x000000AAU 270 #define OB_RDP_LEVEL_1 0x000000BBU 271 #define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2 272 it's no more possible to go back to level 1 or 0 */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type 278 * @{ 279 */ 280 #define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */ 281 #define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ 282 #define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ 283 #define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ 284 #define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ 285 #define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ 286 #define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ 287 #define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ 288 #define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< Boot configuration */ 289 #define OB_USER_SRAM2PE FLASH_OPTR_SRAM2PE /*!< SRAM2 parity check enable */ 290 #define OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST /*!< SRAM2 erase when system reset */ 291 #define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */ 292 #define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ 293 #define OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM /*!< Automatic Gain Control Trimming */ 294 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ 295 OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ 296 OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ 297 OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \ 298 OB_USER_nBOOT0 | OB_USER_AGC_TRIM) /*!< all option bits */ 299 300 /** 301 * @} 302 */ 303 304 /** @defgroup FLASH_OB_USER_AGC_TRIM FLASH Option Bytes Automatic Gain Control Trimming 305 * @{ 306 */ 307 #define OB_AGC_TRIM_0 0x00000000U /*!< Automatic Gain Control Trimming Value 0 */ 308 #define OB_AGC_TRIM_1 FLASH_OPTR_AGC_TRIM_0 /*!< Automatic Gain Control Trimming Value 1 */ 309 #define OB_AGC_TRIM_2 FLASH_OPTR_AGC_TRIM_1 /*!< Automatic Gain Control Trimming Value 2 */ 310 #define OB_AGC_TRIM_3 (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 3 */ 311 #define OB_AGC_TRIM_4 FLASH_OPTR_AGC_TRIM_2 /*!< Automatic Gain Control Trimming Value 4 */ 312 #define OB_AGC_TRIM_5 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 5 */ 313 #define OB_AGC_TRIM_6 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1) /*!< Automatic Gain Control Trimming Value 6 */ 314 #define OB_AGC_TRIM_7 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 7 */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 320 * @{ 321 */ 322 #define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold is around 1.7V */ 323 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 2.0V */ 324 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.2V */ 325 #define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */ 326 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.8V */ 327 /** 328 * @} 329 */ 330 331 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 332 * @{ 333 */ 334 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ 335 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ 336 /** 337 * @} 338 */ 339 340 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 341 * @{ 342 */ 343 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ 344 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 350 * @{ 351 */ 352 #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ 353 #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 359 * @{ 360 */ 361 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 362 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ 363 /** 364 * @} 365 */ 366 367 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 368 * @{ 369 */ 370 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ 371 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ 372 /** 373 * @} 374 */ 375 376 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 377 * @{ 378 */ 379 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ 380 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ 381 /** 382 * @} 383 */ 384 385 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 386 * @{ 387 */ 388 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 389 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ 390 /** 391 * @} 392 */ 393 394 /** @defgroup FLASH_OB_USER_SRAM2PE FLASH Option Bytes SRAM2 parity check 395 * @{ 396 */ 397 #define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity check enable */ 398 #define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2PE /*!< SRAM2 parity check disable */ 399 /** 400 * @} 401 */ 402 403 /** @defgroup FLASH_OB_USER_SRAM2RST FLASH Option Bytes SRAM2 erase when system reset 404 * @{ 405 */ 406 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset */ 407 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2RST /*!< SRAM2 is not erased when a system reset */ 408 /** 409 * @} 410 */ 411 412 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type 413 * @{ 414 */ 415 #define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space (if BOOT0=1) */ 416 #define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 422 * @{ 423 */ 424 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ 425 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PH3/BOOT0 pin */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 431 * @{ 432 */ 433 #define OB_BOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ 434 #define OB_BOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ 435 /** 436 * @} 437 */ 438 439 /** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE 440 * @{ 441 */ 442 #define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */ 443 #define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */ 444 /** 445 * @} 446 */ 447 448 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type 449 * @{ 450 */ 451 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level 452 is decreased from Level 1 to Level 0 */ 453 #define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is 454 decreased from Level 1 to Level 0 (full mass erase) */ 455 /** 456 * @} 457 */ 458 459 /** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode 460 * @{ 461 */ 462 #define SYSTEM_NOT_IN_SECURE_MODE 0x00000000U /*!< Unsecure mode: Security disabled */ 463 #define SYSTEM_IN_SECURE_MODE FLASH_OPTR_ESE /*!< Secure mode : Security enabled */ 464 /** 465 * @} 466 */ 467 468 /** @defgroup C2_FLASH_OB_BOOT_REGION CPU2 Option Bytes Reset Boot Vector 469 * @{ 470 */ 471 #define OB_C2_BOOT_FROM_SRAM 0x00000000U /*!< CPU2 boot from Sram */ 472 #define OB_C2_BOOT_FROM_FLASH FLASH_SRRVR_C2OPT /*!< CPU2 boot from Flash */ 473 /** 474 * @} 475 */ 476 /** 477 * @} 478 */ 479 480 /** @defgroup FLASH_SRAM2A_ADDRESS_RANGE RAM2A address range in secure mode 481 * @{ 482 */ 483 484 #define SRAM2A_START_SECURE_ADDR_0 (SRAM2A_BASE + 0x0000U) /* When in secure mode (SRAM2A_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 485 #define SRAM2A_START_SECURE_ADDR_1 (SRAM2A_BASE + 0x0400U) /* When in secure mode (SRAM2A_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 486 #define SRAM2A_START_SECURE_ADDR_2 (SRAM2A_BASE + 0x0800U) /* When in secure mode (SRAM2A_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 487 #define SRAM2A_START_SECURE_ADDR_3 (SRAM2A_BASE + 0x0C00U) /* When in secure mode (SRAM2A_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 488 #define SRAM2A_START_SECURE_ADDR_4 (SRAM2A_BASE + 0x1000U) /* When in secure mode (SRAM2A_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 489 #define SRAM2A_START_SECURE_ADDR_5 (SRAM2A_BASE + 0x1400U) /* When in secure mode (SRAM2A_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 490 #define SRAM2A_START_SECURE_ADDR_6 (SRAM2A_BASE + 0x1800U) /* When in secure mode (SRAM2A_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 491 #define SRAM2A_START_SECURE_ADDR_7 (SRAM2A_BASE + 0x1C00U) /* When in secure mode (SRAM2A_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 492 #define SRAM2A_START_SECURE_ADDR_8 (SRAM2A_BASE + 0x2000U) /* When in secure mode (SRAM2A_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 493 #define SRAM2A_START_SECURE_ADDR_9 (SRAM2A_BASE + 0x2400U) /* When in secure mode (SRAM2A_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 494 #define SRAM2A_START_SECURE_ADDR_10 (SRAM2A_BASE + 0x2800U) /* When in secure mode (SRAM2A_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 495 #define SRAM2A_START_SECURE_ADDR_11 (SRAM2A_BASE + 0x2C00U) /* When in secure mode (SRAM2A_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 496 #define SRAM2A_START_SECURE_ADDR_12 (SRAM2A_BASE + 0x3000U) /* When in secure mode (SRAM2A_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 497 #define SRAM2A_START_SECURE_ADDR_13 (SRAM2A_BASE + 0x3400U) /* When in secure mode (SRAM2A_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 498 #define SRAM2A_START_SECURE_ADDR_14 (SRAM2A_BASE + 0x3800U) /* When in secure mode (SRAM2A_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 499 #define SRAM2A_START_SECURE_ADDR_15 (SRAM2A_BASE + 0x3C00U) /* When in secure mode (SRAM2A_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 500 #define SRAM2A_START_SECURE_ADDR_16 (SRAM2A_BASE + 0x4000U) /* When in secure mode (SRAM2A_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 501 #define SRAM2A_START_SECURE_ADDR_17 (SRAM2A_BASE + 0x4400U) /* When in secure mode (SRAM2A_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 502 #define SRAM2A_START_SECURE_ADDR_18 (SRAM2A_BASE + 0x4800U) /* When in secure mode (SRAM2A_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 503 #define SRAM2A_START_SECURE_ADDR_19 (SRAM2A_BASE + 0x4C00U) /* When in secure mode (SRAM2A_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 504 #define SRAM2A_START_SECURE_ADDR_20 (SRAM2A_BASE + 0x5000U) /* When in secure mode (SRAM2A_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 505 #define SRAM2A_START_SECURE_ADDR_21 (SRAM2A_BASE + 0x5400U) /* When in secure mode (SRAM2A_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 506 #define SRAM2A_START_SECURE_ADDR_22 (SRAM2A_BASE + 0x5800U) /* When in secure mode (SRAM2A_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 507 #define SRAM2A_START_SECURE_ADDR_23 (SRAM2A_BASE + 0x5C00U) /* When in secure mode (SRAM2A_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 508 #define SRAM2A_START_SECURE_ADDR_24 (SRAM2A_BASE + 0x6000U) /* When in secure mode (SRAM2A_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 509 #define SRAM2A_START_SECURE_ADDR_25 (SRAM2A_BASE + 0x6400U) /* When in secure mode (SRAM2A_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 510 #define SRAM2A_START_SECURE_ADDR_26 (SRAM2A_BASE + 0x6800U) /* When in secure mode (SRAM2A_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 511 #define SRAM2A_START_SECURE_ADDR_27 (SRAM2A_BASE + 0x6C00U) /* When in secure mode (SRAM2A_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 512 #define SRAM2A_START_SECURE_ADDR_28 (SRAM2A_BASE + 0x7000U) /* When in secure mode (SRAM2A_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 513 #define SRAM2A_START_SECURE_ADDR_29 (SRAM2A_BASE + 0x7400U) /* When in secure mode (SRAM2A_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 514 #define SRAM2A_START_SECURE_ADDR_30 (SRAM2A_BASE + 0x7800U) /* When in secure mode (SRAM2A_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 515 #define SRAM2A_START_SECURE_ADDR_31 (SRAM2A_BASE + 0x7C00U) /* When in secure mode (SRAM2A_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 516 #define SRAM2A_FULL_UNSECURE (SRAM2A_BASE + 0x8000U) /* The RAM2A is accessible to M0 Plus and M4 */ 517 518 /** 519 * @} 520 */ 521 522 /** @defgroup FLASH_SRAM2B_ADDRESS_RANGE RAM2B address range in secure mode 523 * @{ 524 */ 525 526 #define SRAM2B_START_SECURE_ADDR_0 (SRAM2B_BASE + 0x0000U) /* When in secure mode (SRAM2B_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 527 #define SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 528 #define SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 529 #define SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 530 #define SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 531 #define SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 532 #define SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 533 #define SRAM2B_START_SECURE_ADDR_7 (SRAM2B_BASE + 0x1C00U) /* When in secure mode (SRAM2B_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 534 #define SRAM2B_START_SECURE_ADDR_8 (SRAM2B_BASE + 0x2000U) /* When in secure mode (SRAM2B_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 535 #define SRAM2B_START_SECURE_ADDR_9 (SRAM2B_BASE + 0x2400U) /* When in secure mode (SRAM2B_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 536 #define SRAM2B_START_SECURE_ADDR_10 (SRAM2B_BASE + 0x2800U) /* When in secure mode (SRAM2B_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 537 #define SRAM2B_START_SECURE_ADDR_11 (SRAM2B_BASE + 0x2C00U) /* When in secure mode (SRAM2B_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 538 #define SRAM2B_START_SECURE_ADDR_12 (SRAM2B_BASE + 0x3000U) /* When in secure mode (SRAM2B_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 539 #define SRAM2B_START_SECURE_ADDR_13 (SRAM2B_BASE + 0x3400U) /* When in secure mode (SRAM2B_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 540 #define SRAM2B_START_SECURE_ADDR_14 (SRAM2B_BASE + 0x3800U) /* When in secure mode (SRAM2B_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 541 #define SRAM2B_START_SECURE_ADDR_15 (SRAM2B_BASE + 0x3C00U) /* When in secure mode (SRAM2B_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 542 #define SRAM2B_START_SECURE_ADDR_16 (SRAM2B_BASE + 0x4000U) /* When in secure mode (SRAM2B_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 543 #define SRAM2B_START_SECURE_ADDR_17 (SRAM2B_BASE + 0x4400U) /* When in secure mode (SRAM2B_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 544 #define SRAM2B_START_SECURE_ADDR_18 (SRAM2B_BASE + 0x4800U) /* When in secure mode (SRAM2B_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 545 #define SRAM2B_START_SECURE_ADDR_19 (SRAM2B_BASE + 0x4C00U) /* When in secure mode (SRAM2B_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 546 #define SRAM2B_START_SECURE_ADDR_20 (SRAM2B_BASE + 0x5000U) /* When in secure mode (SRAM2B_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 547 #define SRAM2B_START_SECURE_ADDR_21 (SRAM2B_BASE + 0x5400U) /* When in secure mode (SRAM2B_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 548 #define SRAM2B_START_SECURE_ADDR_22 (SRAM2B_BASE + 0x5800U) /* When in secure mode (SRAM2B_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 549 #define SRAM2B_START_SECURE_ADDR_23 (SRAM2B_BASE + 0x5C00U) /* When in secure mode (SRAM2B_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 550 #define SRAM2B_START_SECURE_ADDR_24 (SRAM2B_BASE + 0x6000U) /* When in secure mode (SRAM2B_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 551 #define SRAM2B_START_SECURE_ADDR_25 (SRAM2B_BASE + 0x6400U) /* When in secure mode (SRAM2B_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 552 #define SRAM2B_START_SECURE_ADDR_26 (SRAM2B_BASE + 0x6800U) /* When in secure mode (SRAM2B_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 553 #define SRAM2B_START_SECURE_ADDR_27 (SRAM2B_BASE + 0x6C00U) /* When in secure mode (SRAM2B_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 554 #define SRAM2B_START_SECURE_ADDR_28 (SRAM2B_BASE + 0x7000U) /* When in secure mode (SRAM2B_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 555 #define SRAM2B_START_SECURE_ADDR_29 (SRAM2B_BASE + 0x7400U) /* When in secure mode (SRAM2B_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 556 #define SRAM2B_START_SECURE_ADDR_30 (SRAM2B_BASE + 0x7800U) /* When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 557 #define SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ 558 #define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */ 559 560 /** 561 * @} 562 */ 563 564 /** 565 * @} 566 */ 567 568 /* Exported macros -----------------------------------------------------------*/ 569 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 570 * @brief macros to control FLASH features 571 * @{ 572 */ 573 574 /** 575 * @brief Set the FLASH Latency. 576 * @param __LATENCY__ FLASH Latency 577 * This parameter can be one of the following values : 578 * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state 579 * @arg @ref FLASH_LATENCY_1 FLASH One wait state 580 * @arg @ref FLASH_LATENCY_2 FLASH Two wait states 581 * @arg @ref FLASH_LATENCY_3 FLASH Three wait states 582 * @retval None 583 */ 584 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) 585 586 /** 587 * @brief Get the FLASH Latency. 588 * @retval FLASH Latency 589 * Returned value can be one of the following values : 590 * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state 591 * @arg @ref FLASH_LATENCY_1 FLASH One wait state 592 * @arg @ref FLASH_LATENCY_2 FLASH Two wait states 593 * @arg @ref FLASH_LATENCY_3 FLASH Three wait states 594 */ 595 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 596 597 /** 598 * @brief Enable the FLASH prefetch buffer. 599 * @retval None 600 */ 601 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 602 603 /** 604 * @brief Disable the FLASH prefetch buffer. 605 * @retval None 606 */ 607 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 608 609 /** 610 * @brief Enable the FLASH instruction cache. 611 * @retval none 612 */ 613 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) 614 615 /** 616 * @brief Disable the FLASH instruction cache. 617 * @retval none 618 */ 619 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) 620 621 /** 622 * @brief Enable the FLASH data cache. 623 * @retval none 624 */ 625 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) 626 627 /** 628 * @brief Disable the FLASH data cache. 629 * @retval none 630 */ 631 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) 632 633 /** 634 * @brief Reset the FLASH instruction Cache. 635 * @note This function must be used only when the Instruction Cache is disabled. 636 * @retval None 637 */ 638 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 639 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 640 } while (0) 641 642 /** 643 * @brief Reset the FLASH data Cache. 644 * @note This function must be used only when the data Cache is disabled. 645 * @retval None 646 */ 647 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 648 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 649 } while (0) 650 651 /** 652 * @} 653 */ 654 655 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 656 * @brief macros to handle FLASH interrupts 657 * @{ 658 */ 659 660 /** 661 * @brief Enable the specified FLASH interrupt. 662 * @param __INTERRUPT__ FLASH interrupt 663 * This parameter can be any combination of the following values: 664 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 665 * @arg @ref FLASH_IT_OPERR Error Interrupt 666 * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt 667 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 668 * @retval none 669 */ 670 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ 671 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 672 } while(0) 673 674 /** 675 * @brief Disable the specified FLASH interrupt. 676 * @param __INTERRUPT__ FLASH interrupt 677 * This parameter can be any combination of the following values: 678 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 679 * @arg @ref FLASH_IT_OPERR Error Interrupt 680 * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt 681 * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt 682 * @retval none 683 */ 684 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\ 685 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 686 } while(0) 687 688 /** 689 * @brief Check whether the specified FLASH flag is set or not. 690 * @param __FLAG__ specifies the FLASH flag to check. 691 * This parameter can be one of the following values: 692 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 693 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 694 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 695 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 696 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 697 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 698 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 699 * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag 700 * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag 701 * @arg @ref FLASH_FLAG_OPTNV FLASH User Option OPTVAL indication 702 * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag 703 * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag 704 * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag 705 * @arg @ref FLASH_FLAG_CFGBSY Programming/erase configuration busy 706 * @arg @ref FLASH_FLAG_PESD FLASH Programming/erase operation suspended 707 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 708 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 709 * @retval The new state of FLASH_FLAG (SET or RESET). 710 */ 711 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \ 712 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 713 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) 714 /** 715 * @brief Clear the FLASH's pending flags. 716 * @param __FLAG__ specifies the FLASH flags to clear. 717 * This parameter can be any combination of the following values: 718 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 719 * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag 720 * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag 721 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag 722 * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag 723 * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag 724 * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag 725 * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag 726 * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag 727 * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag 728 * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag 729 * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected 730 * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected 731 * @arg @ref FLASH_FLAG_SR_ERRORS FLASH All SR errors flags 732 * @arg @ref FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags 733 * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags 734 * @retval None 735 */ 736 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\ 737 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 738 } while(0) 739 /** 740 * @} 741 */ 742 743 /* Include FLASH HAL Extended module */ 744 #include "stm32wbxx_hal_flash_ex.h" 745 /* Exported variables --------------------------------------------------------*/ 746 /** @defgroup FLASH_Exported_Variables FLASH Exported Variables 747 * @{ 748 */ 749 extern FLASH_ProcessTypeDef pFlash; 750 /** 751 * @} 752 */ 753 754 /* Exported functions --------------------------------------------------------*/ 755 /** @addtogroup FLASH_Exported_Functions 756 * @{ 757 */ 758 759 /* Program operation functions ***********************************************/ 760 /** @addtogroup FLASH_Exported_Functions_Group1 761 * @{ 762 */ 763 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 764 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 765 /* FLASH IRQ handler method */ 766 void HAL_FLASH_IRQHandler(void); 767 /* Callbacks in non blocking modes */ 768 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 769 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 770 /** 771 * @} 772 */ 773 774 /* Peripheral Control functions **********************************************/ 775 /** @addtogroup FLASH_Exported_Functions_Group2 776 * @{ 777 */ 778 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 779 HAL_StatusTypeDef HAL_FLASH_Lock(void); 780 /* Option bytes control */ 781 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 782 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 783 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 784 /** 785 * @} 786 */ 787 788 /* Peripheral State functions ************************************************/ 789 /** @addtogroup FLASH_Exported_Functions_Group3 790 * @{ 791 */ 792 uint32_t HAL_FLASH_GetError(void); 793 /** 794 * @} 795 */ 796 797 /** 798 * @} 799 */ 800 801 /* Private types --------------------------------------------------------*/ 802 /** @defgroup FLASH_Private_types FLASH Private Types 803 * @{ 804 */ 805 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 806 /** 807 * @} 808 */ 809 810 /* Private constants --------------------------------------------------------*/ 811 /** @defgroup FLASH_Private_Constants FLASH Private Constants 812 * @{ 813 */ 814 #define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U) 815 816 #define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */ 817 #define FLASH_PAGE_SIZE 0x00001000U /*!< FLASH Page Size, 4 KBytes */ 818 #define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) 819 #define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ 820 821 #define FLASH_PCROP_GRANULARITY_OFFSET 11U /*!< FLASH Code Readout Protection granularity offset */ 822 #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 2 KBytes */ 823 824 #define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */ 825 /** 826 * @} 827 */ 828 829 /** @defgroup SRAM_MEMORY_SIZE SRAM memory size 830 * @{ 831 */ 832 #define SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U /*!< Secure SRAM2A and SRAM2B Protection granularity offset */ 833 #define SRAM_SECURE_PAGE_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< Secure SRAM2A and SRAM2B Protection granularity, 1KBytes */ 834 /** 835 * @} 836 */ 837 838 /* Private macros ------------------------------------------------------------*/ 839 /** @defgroup FLASH_Private_Macros FLASH Private Macros 840 * @{ 841 */ 842 #define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) 843 844 #define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL)) 845 846 #define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) 847 848 #define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) 849 850 #define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)) 851 852 #define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB) 853 854 #define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL)) 855 856 #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ 857 ((__VALUE__) == FLASH_TYPEERASE_MASSERASE)) 858 859 #define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 860 ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) 861 862 #define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__))) 863 #define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) 864 #define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) 865 #define IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE)) 866 867 #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ 868 OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE))) 869 870 #define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB)) 871 872 #define IS_OB_RDP_LEVEL(__VALUE__) (((__VALUE__) == OB_RDP_LEVEL_0) ||\ 873 ((__VALUE__) == OB_RDP_LEVEL_1) ||\ 874 ((__VALUE__) == OB_RDP_LEVEL_2)) 875 876 #define IS_OB_USER_TYPE(__VALUE__) ((((__VALUE__) & OB_USER_ALL) != 0U) && \ 877 (((__VALUE__) & ~OB_USER_ALL) == 0U)) 878 879 #define IS_OB_USER_CONFIG(__TYPE__, __VALUE__) ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \ 880 ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \ 881 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \ 882 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \ 883 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \ 884 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \ 885 : ((((__TYPE__) & OB_USER_AGC_TRIM) == OB_USER_AGC_TRIM) \ 886 ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_0) || \ 887 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_1) || \ 888 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_2) || \ 889 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_3) || \ 890 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_4) || \ 891 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_5) || \ 892 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_6) || \ 893 (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_7)) \ 894 : ((~(__TYPE__) & (__VALUE__)) == 0U))) 895 896 #define IS_OB_USER_AGC_TRIMMING(__VALUE__) (((__VALUE__) == OB_AGC_TRIM_0) || ((__VALUE__) == OB_AGC_TRIM_1) || \ 897 ((__VALUE__) == OB_AGC_TRIM_2) || ((__VALUE__) == OB_AGC_TRIM_3) || \ 898 ((__VALUE__) == OB_AGC_TRIM_4) || ((__VALUE__) == OB_AGC_TRIM_5) || \ 899 ((__VALUE__) == OB_AGC_TRIM_6) || ((__VALUE__) == OB_AGC_TRIM_7)) 900 901 #define IS_OB_USER_BOR_LEVEL(__VALUE__) (((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \ 902 ((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \ 903 ((__VALUE__) == OB_BOR_LEVEL_4)) 904 905 #define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U) 906 907 #define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__)) 908 909 #define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) ((((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1U))) || \ 910 (((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE - 1U))) || \ 911 (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U))) || \ 912 (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)))) 913 914 #define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM)) 915 916 #define IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U) 917 918 #define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \ 919 ((__VALUE__) == FLASH_LATENCY_1) || \ 920 ((__VALUE__) == FLASH_LATENCY_2) || \ 921 ((__VALUE__) == FLASH_LATENCY_3)) 922 /** 923 * @} 924 */ 925 926 /** 927 * @} 928 */ 929 930 /** 931 * @} 932 */ 933 934 #ifdef __cplusplus 935 } 936 #endif 937 938 #endif /* STM32WBxx_HAL_FLASH_H */ 939 940 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 941