1 /* generated configuration header file - do not edit */ 2 #ifndef BSP_MCU_FAMILY_CFG_H_ 3 #define BSP_MCU_FAMILY_CFG_H_ 4 #include "bsp_mcu_device_pn_cfg.h" 5 #include "bsp_mcu_device_cfg.h" 6 #include "../../../synergy/ssp/src/bsp/mcu/s1ja/bsp_mcu_info.h" 7 #include "bsp_clock_cfg.h" 8 #define BSP_MCU_GROUP_S1JA (1) 9 #define BSP_LOCO_HZ (32768) 10 #define BSP_MOCO_HZ (8000000) 11 #define BSP_SUB_CLOCK_HZ (32768) 12 #if BSP_CFG_HOCO_FREQUENCY == 0 13 #define BSP_HOCO_HZ (24000000) 14 #elif BSP_CFG_HOCO_FREQUENCY == 2 15 #define BSP_HOCO_HZ (32000000) 16 #elif BSP_CFG_HOCO_FREQUENCY == 4 17 #define BSP_HOCO_HZ (48000000) 18 #elif BSP_CFG_HOCO_FREQUENCY == 5 19 #define BSP_HOCO_HZ (64000000) 20 #else 21 #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" 22 #endif 23 24 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) 25 #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) 26 27 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) 28 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) 29 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) 30 #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) 31 #define OFS_SEQ5 (1 << 28) | (1 << 30) 32 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) 33 #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (1 << 8)) 34 #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) 35 #define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC) 36 #define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF) 37 #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) 38 #define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC) 39 #define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF) 40 #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) 41 #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC) 42 #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF) 43 #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) 44 #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) 45 #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) 46 #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) 47 #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) 48 #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x400DFFFF) 49 #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) 50 #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) 51 #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) 52 #endif /* BSP_MCU_FAMILY_CFG_H_ */ 53