1 #ifndef __BDK_CSRS_ECAM_H__
2 #define __BDK_CSRS_ECAM_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
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15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
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21
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24 * derived from this software without specific prior written
25 * permission.
26
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31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium ECAM.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration ecam_bar_e
57 *
58 * ECAM Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_ECAM_BAR_E_ECAMX_PF_BAR0(a) (0x87e048000000ll + 0x1000000ll * (a))
62 #define BDK_ECAM_BAR_E_ECAMX_PF_BAR0_SIZE 0x100000ull
63 #define BDK_ECAM_BAR_E_ECAMX_PF_BAR2(a) (0x848000000000ll + 0x1000000000ll * (a))
64 #define BDK_ECAM_BAR_E_ECAMX_PF_BAR2_SIZE 0x1000000000ull
65
66 /**
67 * Structure ecam_cfg_addr_s
68 *
69 * ECAM Configuration Address Structure
70 * ECAM load and store operations form an address with this structure: 8-bit, 16-bit, 32-bit and
71 * 64-bit read and write operations are supported to this region.
72 */
73 union bdk_ecam_cfg_addr_s
74 {
75 uint64_t u;
76 struct bdk_ecam_cfg_addr_s_s
77 {
78 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
79 uint64_t reserved_52_63 : 12;
80 uint64_t io : 5; /**< [ 51: 47] Indicates I/O space. */
81 uint64_t reserved_46 : 1;
82 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
83 uint64_t did : 8; /**< [ 43: 36] ECAM(0..3) DID. 0x48 + ECAM number. */
84 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
85 Internal:
86 Reserved for future use - Setup. Allow certain PCC
87 configuration registers to be written for boot-time initialization. Treated as 0
88 unless in secure mode. */
89 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
90 Internal:
91 Reserved for future use - Broadcast. Write to all PCC
92 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
93 set. */
94 uint64_t dmn : 6; /**< [ 33: 28] Domain number.
95 Internal:
96 \<33:32\> is SMMU number, \<31:28\> is the bus-numbering space within the SMMU (0x0 or PEM
97 ID). */
98 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
99 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
100 support ARI this contains both the device and function number. */
101 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
102 #else /* Word 0 - Little Endian */
103 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
104 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
105 support ARI this contains both the device and function number. */
106 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
107 uint64_t dmn : 6; /**< [ 33: 28] Domain number.
108 Internal:
109 \<33:32\> is SMMU number, \<31:28\> is the bus-numbering space within the SMMU (0x0 or PEM
110 ID). */
111 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
112 Internal:
113 Reserved for future use - Broadcast. Write to all PCC
114 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
115 set. */
116 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
117 Internal:
118 Reserved for future use - Setup. Allow certain PCC
119 configuration registers to be written for boot-time initialization. Treated as 0
120 unless in secure mode. */
121 uint64_t did : 8; /**< [ 43: 36] ECAM(0..3) DID. 0x48 + ECAM number. */
122 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
123 uint64_t reserved_46 : 1;
124 uint64_t io : 5; /**< [ 51: 47] Indicates I/O space. */
125 uint64_t reserved_52_63 : 12;
126 #endif /* Word 0 - End */
127 } s;
128 struct bdk_ecam_cfg_addr_s_cn9
129 {
130 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
131 uint64_t reserved_52_63 : 12;
132 uint64_t io : 5; /**< [ 51: 47] Indicates I/O space. */
133 uint64_t reserved_46 : 1;
134 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
135 uint64_t did : 8; /**< [ 43: 36] ECAM(0) DID. 0x48. */
136 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
137 Internal:
138 This was intended to allow certain PCC configuration registers to be written for
139 boot-time initialization. Treated as 0 unless in secure mode.
140
141 PEM also uses this flag to write certain CS2 registers, e.g. PCIEEP_BAR0_MASKL,
142 but software should be using PEM()_CFG_WR instead of the ECAM for that. */
143 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
144 Internal:
145 Reserved for future use - Broadcast. Write to all PCC
146 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
147 set. */
148 uint64_t dmn : 6; /**< [ 33: 28] Domain number.
149 Internal:
150 \<33:32\> is SMMU number, \<31:28\> is the bus-numbering space within the SMMU (0x0 or PEM
151 ID). */
152 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
153 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
154 support ARI this contains both the device and function number. */
155 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
156 #else /* Word 0 - Little Endian */
157 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
158 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
159 support ARI this contains both the device and function number. */
160 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
161 uint64_t dmn : 6; /**< [ 33: 28] Domain number.
162 Internal:
163 \<33:32\> is SMMU number, \<31:28\> is the bus-numbering space within the SMMU (0x0 or PEM
164 ID). */
165 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
166 Internal:
167 Reserved for future use - Broadcast. Write to all PCC
168 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
169 set. */
170 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
171 Internal:
172 This was intended to allow certain PCC configuration registers to be written for
173 boot-time initialization. Treated as 0 unless in secure mode.
174
175 PEM also uses this flag to write certain CS2 registers, e.g. PCIEEP_BAR0_MASKL,
176 but software should be using PEM()_CFG_WR instead of the ECAM for that. */
177 uint64_t did : 8; /**< [ 43: 36] ECAM(0) DID. 0x48. */
178 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
179 uint64_t reserved_46 : 1;
180 uint64_t io : 5; /**< [ 51: 47] Indicates I/O space. */
181 uint64_t reserved_52_63 : 12;
182 #endif /* Word 0 - End */
183 } cn9;
184 struct bdk_ecam_cfg_addr_s_cn81xx
185 {
186 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
187 uint64_t reserved_48_63 : 16;
188 uint64_t io : 1; /**< [ 47: 47] Indicates I/O space. */
189 uint64_t reserved_46 : 1;
190 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
191 uint64_t did : 8; /**< [ 43: 36] ECAM(0) DID. 0x48 + ECAM number. */
192 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
193 Internal:
194 Reserved for future use - Setup. Allow certain PCC
195 configuration registers to be written for boot-time initialization. Treated as 0
196 unless in secure mode. */
197 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
198 Internal:
199 Reserved for future use - Broadcast. Write to all PCC
200 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
201 set. */
202 uint64_t reserved_28_33 : 6;
203 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
204 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
205 support ARI this contains both the device and function number. */
206 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
207 #else /* Word 0 - Little Endian */
208 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
209 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
210 support ARI this contains both the device and function number. */
211 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
212 uint64_t reserved_28_33 : 6;
213 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
214 Internal:
215 Reserved for future use - Broadcast. Write to all PCC
216 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
217 set. */
218 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
219 Internal:
220 Reserved for future use - Setup. Allow certain PCC
221 configuration registers to be written for boot-time initialization. Treated as 0
222 unless in secure mode. */
223 uint64_t did : 8; /**< [ 43: 36] ECAM(0) DID. 0x48 + ECAM number. */
224 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
225 uint64_t reserved_46 : 1;
226 uint64_t io : 1; /**< [ 47: 47] Indicates I/O space. */
227 uint64_t reserved_48_63 : 16;
228 #endif /* Word 0 - End */
229 } cn81xx;
230 struct bdk_ecam_cfg_addr_s_cn88xx
231 {
232 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
233 uint64_t reserved_48_63 : 16;
234 uint64_t io : 1; /**< [ 47: 47] Indicates I/O space. */
235 uint64_t reserved_46 : 1;
236 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
237 uint64_t did : 8; /**< [ 43: 36] ECAM(0..3) DID. 0x48 + ECAM number. */
238 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
239 Internal:
240 Reserved for future use - Setup. Allow certain PCC
241 configuration registers to be written for boot-time initialization. Treated as 0
242 unless in secure mode. */
243 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
244 Internal:
245 Reserved for future use - Broadcast. Write to all PCC
246 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
247 set. */
248 uint64_t reserved_28_33 : 6;
249 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
250 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
251 support ARI this contains both the device and function number. */
252 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
253 #else /* Word 0 - Little Endian */
254 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
255 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
256 support ARI this contains both the device and function number. */
257 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
258 uint64_t reserved_28_33 : 6;
259 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
260 Internal:
261 Reserved for future use - Broadcast. Write to all PCC
262 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
263 set. */
264 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
265 Internal:
266 Reserved for future use - Setup. Allow certain PCC
267 configuration registers to be written for boot-time initialization. Treated as 0
268 unless in secure mode. */
269 uint64_t did : 8; /**< [ 43: 36] ECAM(0..3) DID. 0x48 + ECAM number. */
270 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
271 uint64_t reserved_46 : 1;
272 uint64_t io : 1; /**< [ 47: 47] Indicates I/O space. */
273 uint64_t reserved_48_63 : 16;
274 #endif /* Word 0 - End */
275 } cn88xx;
276 struct bdk_ecam_cfg_addr_s_cn83xx
277 {
278 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
279 uint64_t reserved_48_63 : 16;
280 uint64_t io : 1; /**< [ 47: 47] Indicates I/O space. */
281 uint64_t reserved_46 : 1;
282 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
283 uint64_t did : 8; /**< [ 43: 36] ECAM(0..1) DID. 0x48 + ECAM number. */
284 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
285 Internal:
286 Reserved for future use - Setup. Allow certain PCC
287 configuration registers to be written for boot-time initialization. Treated as 0
288 unless in secure mode. */
289 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
290 Internal:
291 Reserved for future use - Broadcast. Write to all PCC
292 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
293 set. */
294 uint64_t reserved_28_33 : 6;
295 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
296 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
297 support ARI this contains both the device and function number. */
298 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
299 #else /* Word 0 - Little Endian */
300 uint64_t addr : 12; /**< [ 11: 0] Register address within the device. */
301 uint64_t func : 8; /**< [ 19: 12] Function number. Note this assumes an ARI device; for external PCI devices that do not
302 support ARI this contains both the device and function number. */
303 uint64_t bus : 8; /**< [ 27: 20] Bus number. */
304 uint64_t reserved_28_33 : 6;
305 uint64_t bcst : 1; /**< [ 34: 34] Reserved, MBZ.
306 Internal:
307 Reserved for future use - Broadcast. Write to all PCC
308 blocks for fast configuration. Treated as 0 unless in secure mode and SETUP is
309 set. */
310 uint64_t setup : 1; /**< [ 35: 35] Reserved, MBZ.
311 Internal:
312 Reserved for future use - Setup. Allow certain PCC
313 configuration registers to be written for boot-time initialization. Treated as 0
314 unless in secure mode. */
315 uint64_t did : 8; /**< [ 43: 36] ECAM(0..1) DID. 0x48 + ECAM number. */
316 uint64_t node : 2; /**< [ 45: 44] CCPI node number. */
317 uint64_t reserved_46 : 1;
318 uint64_t io : 1; /**< [ 47: 47] Indicates I/O space. */
319 uint64_t reserved_48_63 : 16;
320 #endif /* Word 0 - End */
321 } cn83xx;
322 };
323
324 /**
325 * Register (RSL) ecam#_bus#_nsdis
326 *
327 * ECAM Bus Nonsecure Disable Registers
328 */
329 union bdk_ecamx_busx_nsdis
330 {
331 uint64_t u;
332 struct bdk_ecamx_busx_nsdis_s
333 {
334 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
335 uint64_t reserved_1_63 : 63;
336 uint64_t dis : 1; /**< [ 0: 0](R/W) Disable ECAM bus in nonsecure mode. If set, the indexed ECAM bus number is RAO/WI
337 when accessed via the ECAM space with nonsecure transactions. Note this affects only ECAM
338 configuration access, not normal I/O mapped memory accesses to the device. ECAM 0, bus 0
339 (corresponding to RSL devices) is not generally disabled, instead may be used to disable
340 RSL discovery. */
341 #else /* Word 0 - Little Endian */
342 uint64_t dis : 1; /**< [ 0: 0](R/W) Disable ECAM bus in nonsecure mode. If set, the indexed ECAM bus number is RAO/WI
343 when accessed via the ECAM space with nonsecure transactions. Note this affects only ECAM
344 configuration access, not normal I/O mapped memory accesses to the device. ECAM 0, bus 0
345 (corresponding to RSL devices) is not generally disabled, instead may be used to disable
346 RSL discovery. */
347 uint64_t reserved_1_63 : 63;
348 #endif /* Word 0 - End */
349 } s;
350 /* struct bdk_ecamx_busx_nsdis_s cn; */
351 };
352 typedef union bdk_ecamx_busx_nsdis bdk_ecamx_busx_nsdis_t;
353
354 static inline uint64_t BDK_ECAMX_BUSX_NSDIS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_BUSX_NSDIS(unsigned long a,unsigned long b)355 static inline uint64_t BDK_ECAMX_BUSX_NSDIS(unsigned long a, unsigned long b)
356 {
357 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=255)))
358 return 0x87e048030000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0xff);
359 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=255)))
360 return 0x87e048030000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
361 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=255)))
362 return 0x87e048030000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0xff);
363 __bdk_csr_fatal("ECAMX_BUSX_NSDIS", 2, a, b, 0, 0);
364 }
365
366 #define typedef_BDK_ECAMX_BUSX_NSDIS(a,b) bdk_ecamx_busx_nsdis_t
367 #define bustype_BDK_ECAMX_BUSX_NSDIS(a,b) BDK_CSR_TYPE_RSL
368 #define basename_BDK_ECAMX_BUSX_NSDIS(a,b) "ECAMX_BUSX_NSDIS"
369 #define device_bar_BDK_ECAMX_BUSX_NSDIS(a,b) 0x0 /* PF_BAR0 */
370 #define busnum_BDK_ECAMX_BUSX_NSDIS(a,b) (a)
371 #define arguments_BDK_ECAMX_BUSX_NSDIS(a,b) (a),(b),-1,-1
372
373 /**
374 * Register (RSL) ecam#_bus#_sdis
375 *
376 * ECAM Bus Secure Disable Registers
377 */
378 union bdk_ecamx_busx_sdis
379 {
380 uint64_t u;
381 struct bdk_ecamx_busx_sdis_s
382 {
383 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
384 uint64_t reserved_2_63 : 62;
385 uint64_t sec : 1; /**< [ 1: 1](SR/W) Secure ECAM bus. If set, the indexed ECAM bus number is secured and RAO/WI when
386 accessed via the ECAM space with nonsecure transactions. This bit overrides
387 ECAM()_BUS()_NSDIS[DIS]. */
388 uint64_t dis : 1; /**< [ 0: 0](SR/W) Disable ECAM bus in secure mode. If set, the indexed ECAM bus number is RAO/WI when
389 accessed via the ECAM space with secure transactions. This bit is similar to the non-
390 secure ECAM()_BUS()_NSDIS[DIS]. */
391 #else /* Word 0 - Little Endian */
392 uint64_t dis : 1; /**< [ 0: 0](SR/W) Disable ECAM bus in secure mode. If set, the indexed ECAM bus number is RAO/WI when
393 accessed via the ECAM space with secure transactions. This bit is similar to the non-
394 secure ECAM()_BUS()_NSDIS[DIS]. */
395 uint64_t sec : 1; /**< [ 1: 1](SR/W) Secure ECAM bus. If set, the indexed ECAM bus number is secured and RAO/WI when
396 accessed via the ECAM space with nonsecure transactions. This bit overrides
397 ECAM()_BUS()_NSDIS[DIS]. */
398 uint64_t reserved_2_63 : 62;
399 #endif /* Word 0 - End */
400 } s;
401 /* struct bdk_ecamx_busx_sdis_s cn; */
402 };
403 typedef union bdk_ecamx_busx_sdis bdk_ecamx_busx_sdis_t;
404
405 static inline uint64_t BDK_ECAMX_BUSX_SDIS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_BUSX_SDIS(unsigned long a,unsigned long b)406 static inline uint64_t BDK_ECAMX_BUSX_SDIS(unsigned long a, unsigned long b)
407 {
408 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=255)))
409 return 0x87e048020000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0xff);
410 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=255)))
411 return 0x87e048020000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
412 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=255)))
413 return 0x87e048020000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0xff);
414 __bdk_csr_fatal("ECAMX_BUSX_SDIS", 2, a, b, 0, 0);
415 }
416
417 #define typedef_BDK_ECAMX_BUSX_SDIS(a,b) bdk_ecamx_busx_sdis_t
418 #define bustype_BDK_ECAMX_BUSX_SDIS(a,b) BDK_CSR_TYPE_RSL
419 #define basename_BDK_ECAMX_BUSX_SDIS(a,b) "ECAMX_BUSX_SDIS"
420 #define device_bar_BDK_ECAMX_BUSX_SDIS(a,b) 0x0 /* PF_BAR0 */
421 #define busnum_BDK_ECAMX_BUSX_SDIS(a,b) (a)
422 #define arguments_BDK_ECAMX_BUSX_SDIS(a,b) (a),(b),-1,-1
423
424 /**
425 * Register (RSL) ecam#_bus#_skill
426 *
427 * ECAM Bus Secure Disable Registers
428 */
429 union bdk_ecamx_busx_skill
430 {
431 uint64_t u;
432 struct bdk_ecamx_busx_skill_s
433 {
434 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
435 uint64_t reserved_1_63 : 63;
436 uint64_t skill : 1; /**< [ 0: 0](SR/W1S) ECAM bus kill.
437 Write one to set. Once set, cannot be cleared until soft reset. If set,
438 the indexed ECAM bus/function/device number is RAO/WI when accessed via
439 the ECAM space with any (secure/nonsecure) transactions. */
440 #else /* Word 0 - Little Endian */
441 uint64_t skill : 1; /**< [ 0: 0](SR/W1S) ECAM bus kill.
442 Write one to set. Once set, cannot be cleared until soft reset. If set,
443 the indexed ECAM bus/function/device number is RAO/WI when accessed via
444 the ECAM space with any (secure/nonsecure) transactions. */
445 uint64_t reserved_1_63 : 63;
446 #endif /* Word 0 - End */
447 } s;
448 /* struct bdk_ecamx_busx_skill_s cn; */
449 };
450 typedef union bdk_ecamx_busx_skill bdk_ecamx_busx_skill_t;
451
452 static inline uint64_t BDK_ECAMX_BUSX_SKILL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_BUSX_SKILL(unsigned long a,unsigned long b)453 static inline uint64_t BDK_ECAMX_BUSX_SKILL(unsigned long a, unsigned long b)
454 {
455 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=255)))
456 return 0x87e048080000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0xff);
457 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=255)))
458 return 0x87e048080000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
459 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && ((a<=3) && (b<=255)))
460 return 0x87e048080000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0xff);
461 __bdk_csr_fatal("ECAMX_BUSX_SKILL", 2, a, b, 0, 0);
462 }
463
464 #define typedef_BDK_ECAMX_BUSX_SKILL(a,b) bdk_ecamx_busx_skill_t
465 #define bustype_BDK_ECAMX_BUSX_SKILL(a,b) BDK_CSR_TYPE_RSL
466 #define basename_BDK_ECAMX_BUSX_SKILL(a,b) "ECAMX_BUSX_SKILL"
467 #define device_bar_BDK_ECAMX_BUSX_SKILL(a,b) 0x0 /* PF_BAR0 */
468 #define busnum_BDK_ECAMX_BUSX_SKILL(a,b) (a)
469 #define arguments_BDK_ECAMX_BUSX_SKILL(a,b) (a),(b),-1,-1
470
471 /**
472 * Register (RSL) ecam#_const
473 *
474 * ECAM Constants Register
475 * This register contains constants for software discovery.
476 */
477 union bdk_ecamx_const
478 {
479 uint64_t u;
480 struct bdk_ecamx_const_s
481 {
482 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
483 uint64_t reserved_16_63 : 48;
484 uint64_t domains : 8; /**< [ 15: 8](RO) Number of domains. */
485 uint64_t ecams : 8; /**< [ 7: 0](RO) Number of ECAM units. */
486 #else /* Word 0 - Little Endian */
487 uint64_t ecams : 8; /**< [ 7: 0](RO) Number of ECAM units. */
488 uint64_t domains : 8; /**< [ 15: 8](RO) Number of domains. */
489 uint64_t reserved_16_63 : 48;
490 #endif /* Word 0 - End */
491 } s;
492 struct bdk_ecamx_const_cn8
493 {
494 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
495 uint64_t reserved_8_63 : 56;
496 uint64_t ecams : 8; /**< [ 7: 0](RO) Number of ECAM units. */
497 #else /* Word 0 - Little Endian */
498 uint64_t ecams : 8; /**< [ 7: 0](RO) Number of ECAM units. */
499 uint64_t reserved_8_63 : 56;
500 #endif /* Word 0 - End */
501 } cn8;
502 /* struct bdk_ecamx_const_s cn9; */
503 };
504 typedef union bdk_ecamx_const bdk_ecamx_const_t;
505
506 static inline uint64_t BDK_ECAMX_CONST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_ECAMX_CONST(unsigned long a)507 static inline uint64_t BDK_ECAMX_CONST(unsigned long a)
508 {
509 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
510 return 0x87e048000200ll + 0x1000000ll * ((a) & 0x0);
511 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
512 return 0x87e048000200ll + 0x1000000ll * ((a) & 0x1);
513 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a==0))
514 return 0x87e048000200ll + 0x1000000ll * ((a) & 0x0);
515 __bdk_csr_fatal("ECAMX_CONST", 1, a, 0, 0, 0);
516 }
517
518 #define typedef_BDK_ECAMX_CONST(a) bdk_ecamx_const_t
519 #define bustype_BDK_ECAMX_CONST(a) BDK_CSR_TYPE_RSL
520 #define basename_BDK_ECAMX_CONST(a) "ECAMX_CONST"
521 #define device_bar_BDK_ECAMX_CONST(a) 0x0 /* PF_BAR0 */
522 #define busnum_BDK_ECAMX_CONST(a) (a)
523 #define arguments_BDK_ECAMX_CONST(a) (a),-1,-1,-1
524
525 /**
526 * Register (RSL) ecam#_dev#_nsdis
527 *
528 * ECAM Device Nonsecure Disable Registers
529 */
530 union bdk_ecamx_devx_nsdis
531 {
532 uint64_t u;
533 struct bdk_ecamx_devx_nsdis_s
534 {
535 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
536 uint64_t reserved_1_63 : 63;
537 uint64_t dis : 1; /**< [ 0: 0](R/W) Disable ECAM device in nonsecure mode. If set, the specified device
538 number on bus 0 are RAO/WI when accessed via the ECAM space with
539 nonsecure transactions. Note this affects only ECAM configuration
540 access, not normal I/O mapped memory accesses to the device. */
541 #else /* Word 0 - Little Endian */
542 uint64_t dis : 1; /**< [ 0: 0](R/W) Disable ECAM device in nonsecure mode. If set, the specified device
543 number on bus 0 are RAO/WI when accessed via the ECAM space with
544 nonsecure transactions. Note this affects only ECAM configuration
545 access, not normal I/O mapped memory accesses to the device. */
546 uint64_t reserved_1_63 : 63;
547 #endif /* Word 0 - End */
548 } s;
549 /* struct bdk_ecamx_devx_nsdis_s cn; */
550 };
551 typedef union bdk_ecamx_devx_nsdis bdk_ecamx_devx_nsdis_t;
552
553 static inline uint64_t BDK_ECAMX_DEVX_NSDIS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_DEVX_NSDIS(unsigned long a,unsigned long b)554 static inline uint64_t BDK_ECAMX_DEVX_NSDIS(unsigned long a, unsigned long b)
555 {
556 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=31)))
557 return 0x87e048070000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0x1f);
558 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=31)))
559 return 0x87e048070000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1f);
560 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=31)))
561 return 0x87e048070000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x1f);
562 __bdk_csr_fatal("ECAMX_DEVX_NSDIS", 2, a, b, 0, 0);
563 }
564
565 #define typedef_BDK_ECAMX_DEVX_NSDIS(a,b) bdk_ecamx_devx_nsdis_t
566 #define bustype_BDK_ECAMX_DEVX_NSDIS(a,b) BDK_CSR_TYPE_RSL
567 #define basename_BDK_ECAMX_DEVX_NSDIS(a,b) "ECAMX_DEVX_NSDIS"
568 #define device_bar_BDK_ECAMX_DEVX_NSDIS(a,b) 0x0 /* PF_BAR0 */
569 #define busnum_BDK_ECAMX_DEVX_NSDIS(a,b) (a)
570 #define arguments_BDK_ECAMX_DEVX_NSDIS(a,b) (a),(b),-1,-1
571
572 /**
573 * Register (RSL) ecam#_dev#_sdis
574 *
575 * ECAM Device Secure Disable Registers
576 */
577 union bdk_ecamx_devx_sdis
578 {
579 uint64_t u;
580 struct bdk_ecamx_devx_sdis_s
581 {
582 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
583 uint64_t reserved_2_63 : 62;
584 uint64_t sec : 1; /**< [ 1: 1](SR/W) Secure ECAM device. If set, the indexed device number on bus 0 are
585 secured and RAO/WI when accessed via the ECAM space with nonsecure
586 transactions. This bit overrides ECAM()_DEV()_NSDIS[DIS]. */
587 uint64_t dis : 1; /**< [ 0: 0](SR/W) Disable ECAM device in secure mode. If set, ECAM secure
588 read/write operations to the indexed device number on bus 0
589 are RAO/WI when accessed via the ECAM space. This bit is
590 similar to the nonsecure ECAM()_DEV()_NSDIS[DIS]. */
591 #else /* Word 0 - Little Endian */
592 uint64_t dis : 1; /**< [ 0: 0](SR/W) Disable ECAM device in secure mode. If set, ECAM secure
593 read/write operations to the indexed device number on bus 0
594 are RAO/WI when accessed via the ECAM space. This bit is
595 similar to the nonsecure ECAM()_DEV()_NSDIS[DIS]. */
596 uint64_t sec : 1; /**< [ 1: 1](SR/W) Secure ECAM device. If set, the indexed device number on bus 0 are
597 secured and RAO/WI when accessed via the ECAM space with nonsecure
598 transactions. This bit overrides ECAM()_DEV()_NSDIS[DIS]. */
599 uint64_t reserved_2_63 : 62;
600 #endif /* Word 0 - End */
601 } s;
602 /* struct bdk_ecamx_devx_sdis_s cn; */
603 };
604 typedef union bdk_ecamx_devx_sdis bdk_ecamx_devx_sdis_t;
605
606 static inline uint64_t BDK_ECAMX_DEVX_SDIS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_DEVX_SDIS(unsigned long a,unsigned long b)607 static inline uint64_t BDK_ECAMX_DEVX_SDIS(unsigned long a, unsigned long b)
608 {
609 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=31)))
610 return 0x87e048060000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0x1f);
611 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=31)))
612 return 0x87e048060000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1f);
613 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=31)))
614 return 0x87e048060000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x1f);
615 __bdk_csr_fatal("ECAMX_DEVX_SDIS", 2, a, b, 0, 0);
616 }
617
618 #define typedef_BDK_ECAMX_DEVX_SDIS(a,b) bdk_ecamx_devx_sdis_t
619 #define bustype_BDK_ECAMX_DEVX_SDIS(a,b) BDK_CSR_TYPE_RSL
620 #define basename_BDK_ECAMX_DEVX_SDIS(a,b) "ECAMX_DEVX_SDIS"
621 #define device_bar_BDK_ECAMX_DEVX_SDIS(a,b) 0x0 /* PF_BAR0 */
622 #define busnum_BDK_ECAMX_DEVX_SDIS(a,b) (a)
623 #define arguments_BDK_ECAMX_DEVX_SDIS(a,b) (a),(b),-1,-1
624
625 /**
626 * Register (RSL) ecam#_dev#_skill
627 *
628 * ECAM Device Secure Disable Registers
629 */
630 union bdk_ecamx_devx_skill
631 {
632 uint64_t u;
633 struct bdk_ecamx_devx_skill_s
634 {
635 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
636 uint64_t reserved_1_63 : 63;
637 uint64_t skill : 1; /**< [ 0: 0](SR/W1S) ECAM device kill.
638 Write one to set. Once set, cannot be cleared until soft reset. If set,
639 the indexed ECAM bus/function/device number is RAO/WI when accessed via
640 the ECAM space with any (secure/nonsecure) transactions. */
641 #else /* Word 0 - Little Endian */
642 uint64_t skill : 1; /**< [ 0: 0](SR/W1S) ECAM device kill.
643 Write one to set. Once set, cannot be cleared until soft reset. If set,
644 the indexed ECAM bus/function/device number is RAO/WI when accessed via
645 the ECAM space with any (secure/nonsecure) transactions. */
646 uint64_t reserved_1_63 : 63;
647 #endif /* Word 0 - End */
648 } s;
649 /* struct bdk_ecamx_devx_skill_s cn; */
650 };
651 typedef union bdk_ecamx_devx_skill bdk_ecamx_devx_skill_t;
652
653 static inline uint64_t BDK_ECAMX_DEVX_SKILL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_DEVX_SKILL(unsigned long a,unsigned long b)654 static inline uint64_t BDK_ECAMX_DEVX_SKILL(unsigned long a, unsigned long b)
655 {
656 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=31)))
657 return 0x87e0480a0000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0x1f);
658 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=31)))
659 return 0x87e0480a0000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x1f);
660 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && ((a<=3) && (b<=31)))
661 return 0x87e0480a0000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x1f);
662 __bdk_csr_fatal("ECAMX_DEVX_SKILL", 2, a, b, 0, 0);
663 }
664
665 #define typedef_BDK_ECAMX_DEVX_SKILL(a,b) bdk_ecamx_devx_skill_t
666 #define bustype_BDK_ECAMX_DEVX_SKILL(a,b) BDK_CSR_TYPE_RSL
667 #define basename_BDK_ECAMX_DEVX_SKILL(a,b) "ECAMX_DEVX_SKILL"
668 #define device_bar_BDK_ECAMX_DEVX_SKILL(a,b) 0x0 /* PF_BAR0 */
669 #define busnum_BDK_ECAMX_DEVX_SKILL(a,b) (a)
670 #define arguments_BDK_ECAMX_DEVX_SKILL(a,b) (a),(b),-1,-1
671
672 /**
673 * Register (RSL) ecam#_dom#_bus#_permit
674 *
675 * ECAM Domain Bus Permit Registers
676 * This register sets the permissions for an ECAM access to a device
677 * using a given ECAM bus number.
678 *
679 * Index {b} corresponds to the ECAM address's domain (address's ECAM_CFG_ADDR_S[DMN]).
680 * ECAM()_DOM()_CONST[PERMIT] is used to discover for which domains this register is
681 * implemented; nonimplemented indices are RAZ.
682 *
683 * Index {c} corresponds to the ECAM address's bus number (address's ECAM_CFG_ADDR_S[BUS]).
684 */
685 union bdk_ecamx_domx_busx_permit
686 {
687 uint64_t u;
688 struct bdk_ecamx_domx_busx_permit_s
689 {
690 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
691 uint64_t reserved_8_63 : 56;
692 uint64_t kill : 1; /**< [ 7: 7](SR/W1S) Kill the device. Once written with one, stays
693 set until warm chip reset. If set, no access
694 allowed by any initiator. */
695 uint64_t reserved_4_6 : 3;
696 uint64_t xcp1_dis : 1; /**< [ 3: 3](SR/W) XCP1 disable. As with [SEC_DIS], but for accesses initiated by XCP1 (MCP). */
697 uint64_t xcp0_dis : 1; /**< [ 2: 2](SR/W) XCP0 disable. As with [SEC_DIS], but for accesses initiated by XCP0 (SCP). */
698 uint64_t nsec_dis : 1; /**< [ 1: 1](SR/W) Nonsecure disable. As with [SEC_DIS], but for accesses initiated by non-secure devices
699 excluding XCP0/XCP1. */
700 uint64_t sec_dis : 1; /**< [ 0: 0](SR/W) Secure disable. */
701 #else /* Word 0 - Little Endian */
702 uint64_t sec_dis : 1; /**< [ 0: 0](SR/W) Secure disable. */
703 uint64_t nsec_dis : 1; /**< [ 1: 1](SR/W) Nonsecure disable. As with [SEC_DIS], but for accesses initiated by non-secure devices
704 excluding XCP0/XCP1. */
705 uint64_t xcp0_dis : 1; /**< [ 2: 2](SR/W) XCP0 disable. As with [SEC_DIS], but for accesses initiated by XCP0 (SCP). */
706 uint64_t xcp1_dis : 1; /**< [ 3: 3](SR/W) XCP1 disable. As with [SEC_DIS], but for accesses initiated by XCP1 (MCP). */
707 uint64_t reserved_4_6 : 3;
708 uint64_t kill : 1; /**< [ 7: 7](SR/W1S) Kill the device. Once written with one, stays
709 set until warm chip reset. If set, no access
710 allowed by any initiator. */
711 uint64_t reserved_8_63 : 56;
712 #endif /* Word 0 - End */
713 } s;
714 /* struct bdk_ecamx_domx_busx_permit_s cn; */
715 };
716 typedef union bdk_ecamx_domx_busx_permit bdk_ecamx_domx_busx_permit_t;
717
718 static inline uint64_t BDK_ECAMX_DOMX_BUSX_PERMIT(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_ECAMX_DOMX_BUSX_PERMIT(unsigned long a,unsigned long b,unsigned long c)719 static inline uint64_t BDK_ECAMX_DOMX_BUSX_PERMIT(unsigned long a, unsigned long b, unsigned long c)
720 {
721 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a==0) && ((b==0) || (b==1) || (b==2)) && (c<=255)))
722 return 0x87e048020000ll + 0x1000000ll * ((a) & 0x0) + 0x800ll * ((b) & 0x3) + 8ll * ((c) & 0xff);
723 __bdk_csr_fatal("ECAMX_DOMX_BUSX_PERMIT", 3, a, b, c, 0);
724 }
725
726 #define typedef_BDK_ECAMX_DOMX_BUSX_PERMIT(a,b,c) bdk_ecamx_domx_busx_permit_t
727 #define bustype_BDK_ECAMX_DOMX_BUSX_PERMIT(a,b,c) BDK_CSR_TYPE_RSL
728 #define basename_BDK_ECAMX_DOMX_BUSX_PERMIT(a,b,c) "ECAMX_DOMX_BUSX_PERMIT"
729 #define device_bar_BDK_ECAMX_DOMX_BUSX_PERMIT(a,b,c) 0x0 /* PF_BAR0 */
730 #define busnum_BDK_ECAMX_DOMX_BUSX_PERMIT(a,b,c) (a)
731 #define arguments_BDK_ECAMX_DOMX_BUSX_PERMIT(a,b,c) (a),(b),(c),-1
732
733 /**
734 * Register (RSL) ecam#_dom#_const
735 *
736 * ECAM Constants Register
737 * This register contains constants for software discovery.
738 *
739 * Index {b} indicates the domain for which the attributes are to be returned.
740 */
741 union bdk_ecamx_domx_const
742 {
743 uint64_t u;
744 struct bdk_ecamx_domx_const_s
745 {
746 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
747 uint64_t reserved_6_63 : 58;
748 uint64_t pres : 1; /**< [ 5: 5](RO) If implemented. */
749 uint64_t permit : 1; /**< [ 4: 4](RO) If set, for this domain number, the ECAM()_DOM()_BUS()_PERMIT,
750 ECAM()_DOM()_RSL()_PERMIT, and ECAM()_DOM()_DEV()_PERMIT registers are implemented. */
751 uint64_t smmu : 4; /**< [ 3: 0](RO) Attached SMMU number. */
752 #else /* Word 0 - Little Endian */
753 uint64_t smmu : 4; /**< [ 3: 0](RO) Attached SMMU number. */
754 uint64_t permit : 1; /**< [ 4: 4](RO) If set, for this domain number, the ECAM()_DOM()_BUS()_PERMIT,
755 ECAM()_DOM()_RSL()_PERMIT, and ECAM()_DOM()_DEV()_PERMIT registers are implemented. */
756 uint64_t pres : 1; /**< [ 5: 5](RO) If implemented. */
757 uint64_t reserved_6_63 : 58;
758 #endif /* Word 0 - End */
759 } s;
760 /* struct bdk_ecamx_domx_const_s cn; */
761 };
762 typedef union bdk_ecamx_domx_const bdk_ecamx_domx_const_t;
763
764 static inline uint64_t BDK_ECAMX_DOMX_CONST(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_DOMX_CONST(unsigned long a,unsigned long b)765 static inline uint64_t BDK_ECAMX_DOMX_CONST(unsigned long a, unsigned long b)
766 {
767 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a==0) && (b<=63)))
768 return 0x87e048000400ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0x3f);
769 __bdk_csr_fatal("ECAMX_DOMX_CONST", 2, a, b, 0, 0);
770 }
771
772 #define typedef_BDK_ECAMX_DOMX_CONST(a,b) bdk_ecamx_domx_const_t
773 #define bustype_BDK_ECAMX_DOMX_CONST(a,b) BDK_CSR_TYPE_RSL
774 #define basename_BDK_ECAMX_DOMX_CONST(a,b) "ECAMX_DOMX_CONST"
775 #define device_bar_BDK_ECAMX_DOMX_CONST(a,b) 0x0 /* PF_BAR0 */
776 #define busnum_BDK_ECAMX_DOMX_CONST(a,b) (a)
777 #define arguments_BDK_ECAMX_DOMX_CONST(a,b) (a),(b),-1,-1
778
779 /**
780 * Register (RSL) ecam#_dom#_dev#_permit
781 *
782 * ECAM Domain Device Permit Registers
783 * This register sets the permissions for a ECAM access to a bus 0 device.
784 * This register is used when the bus number is 0; i.e. address's ECAM_CFG_ADDR_S[BUS] = 0x0.
785 *
786 * Index {b} corresponds to the ECAM address's domain (address's ECAM_CFG_ADDR_S[DOMAIN]).
787 * ECAM()_DOM()_CONST[PERMIT] is used to discover for which domains this register is
788 * implemented; nonimplemented indices are RAZ.
789 *
790 * Index {c} corresponds to the bus 0 non-ARI device number (address's
791 * ECAM_CFG_ADDR_S[FUNC]\<7:3\>).
792 */
793 union bdk_ecamx_domx_devx_permit
794 {
795 uint64_t u;
796 struct bdk_ecamx_domx_devx_permit_s
797 {
798 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
799 uint64_t reserved_8_63 : 56;
800 uint64_t kill : 1; /**< [ 7: 7](SR/W1S) Kill the device. Once written with one, stays
801 set until warm chip reset. If set, no access
802 allowed by any initiator. */
803 uint64_t reserved_4_6 : 3;
804 uint64_t xcp1_dis : 1; /**< [ 3: 3](SR/W) XCP1 disable. As with [SEC_DIS], but for accesses initiated by XCP1 (MCP). */
805 uint64_t xcp0_dis : 1; /**< [ 2: 2](SR/W) XCP0 disable. As with [SEC_DIS], but for accesses initiated by XCP0 (SCP). */
806 uint64_t nsec_dis : 1; /**< [ 1: 1](SR/W) Nonsecure disable. As with [SEC_DIS], but for accesses initiated by non-secure devices
807 excluding XCP0/XCP1. */
808 uint64_t sec_dis : 1; /**< [ 0: 0](SR/W) Secure disable. */
809 #else /* Word 0 - Little Endian */
810 uint64_t sec_dis : 1; /**< [ 0: 0](SR/W) Secure disable. */
811 uint64_t nsec_dis : 1; /**< [ 1: 1](SR/W) Nonsecure disable. As with [SEC_DIS], but for accesses initiated by non-secure devices
812 excluding XCP0/XCP1. */
813 uint64_t xcp0_dis : 1; /**< [ 2: 2](SR/W) XCP0 disable. As with [SEC_DIS], but for accesses initiated by XCP0 (SCP). */
814 uint64_t xcp1_dis : 1; /**< [ 3: 3](SR/W) XCP1 disable. As with [SEC_DIS], but for accesses initiated by XCP1 (MCP). */
815 uint64_t reserved_4_6 : 3;
816 uint64_t kill : 1; /**< [ 7: 7](SR/W1S) Kill the device. Once written with one, stays
817 set until warm chip reset. If set, no access
818 allowed by any initiator. */
819 uint64_t reserved_8_63 : 56;
820 #endif /* Word 0 - End */
821 } s;
822 /* struct bdk_ecamx_domx_devx_permit_s cn; */
823 };
824 typedef union bdk_ecamx_domx_devx_permit bdk_ecamx_domx_devx_permit_t;
825
826 static inline uint64_t BDK_ECAMX_DOMX_DEVX_PERMIT(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_ECAMX_DOMX_DEVX_PERMIT(unsigned long a,unsigned long b,unsigned long c)827 static inline uint64_t BDK_ECAMX_DOMX_DEVX_PERMIT(unsigned long a, unsigned long b, unsigned long c)
828 {
829 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a==0) && ((b==0) || (b==1) || (b==2)) && (c<=31)))
830 return 0x87e048040000ll + 0x1000000ll * ((a) & 0x0) + 0x800ll * ((b) & 0x3) + 8ll * ((c) & 0x1f);
831 __bdk_csr_fatal("ECAMX_DOMX_DEVX_PERMIT", 3, a, b, c, 0);
832 }
833
834 #define typedef_BDK_ECAMX_DOMX_DEVX_PERMIT(a,b,c) bdk_ecamx_domx_devx_permit_t
835 #define bustype_BDK_ECAMX_DOMX_DEVX_PERMIT(a,b,c) BDK_CSR_TYPE_RSL
836 #define basename_BDK_ECAMX_DOMX_DEVX_PERMIT(a,b,c) "ECAMX_DOMX_DEVX_PERMIT"
837 #define device_bar_BDK_ECAMX_DOMX_DEVX_PERMIT(a,b,c) 0x0 /* PF_BAR0 */
838 #define busnum_BDK_ECAMX_DOMX_DEVX_PERMIT(a,b,c) (a)
839 #define arguments_BDK_ECAMX_DOMX_DEVX_PERMIT(a,b,c) (a),(b),(c),-1
840
841 /**
842 * Register (RSL) ecam#_dom#_rsl#_permit
843 *
844 * ECAM Domain Device Permit Registers
845 * This register sets the permissions for an ECAM access to an RSL device.
846 * This register is used when the domain and bus point to RSL; i.e.
847 * address's ECAM_CFG_ADDR_S[DOMAIN]=PCC_DEV_CON_E::PCCBR_MRML\<21:16\>,
848 * ECAM_CFG_ADDR_S[BUS] = PCC_DEV_CON_E::PCCBR_MRML\<15:8\>.
849 *
850 * Index {b} corresponds to the ECAM address's domain (address's ECAM_CFG_ADDR_S[DOMAIN]).
851 * ECAM()_DOM()_CONST[PERMIT] is used to discover for which domains this register is
852 * implemented; nonimplemented indices are RAZ.
853 *
854 * Index {c} corresponds to the RSL device number (address's ECAM_CFG_ADDR_S[FUNC]).
855 */
856 union bdk_ecamx_domx_rslx_permit
857 {
858 uint64_t u;
859 struct bdk_ecamx_domx_rslx_permit_s
860 {
861 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
862 uint64_t reserved_8_63 : 56;
863 uint64_t kill : 1; /**< [ 7: 7](SR/W1S) Kill the device. Once written with one, stays
864 set until warm chip reset. If set, no access
865 allowed by any initiator. */
866 uint64_t reserved_4_6 : 3;
867 uint64_t xcp1_dis : 1; /**< [ 3: 3](SR/W) XCP1 disable. As with [SEC_DIS], but for accesses initiated by XCP1 (MCP). */
868 uint64_t xcp0_dis : 1; /**< [ 2: 2](SR/W) XCP0 disable. As with [SEC_DIS], but for accesses initiated by XCP0 (SCP). */
869 uint64_t nsec_dis : 1; /**< [ 1: 1](SR/W) Nonsecure disable. As with [SEC_DIS], but for accesses initiated by non-secure devices
870 excluding XCP0/XCP1. */
871 uint64_t sec_dis : 1; /**< [ 0: 0](SR/W) Secure disable. */
872 #else /* Word 0 - Little Endian */
873 uint64_t sec_dis : 1; /**< [ 0: 0](SR/W) Secure disable. */
874 uint64_t nsec_dis : 1; /**< [ 1: 1](SR/W) Nonsecure disable. As with [SEC_DIS], but for accesses initiated by non-secure devices
875 excluding XCP0/XCP1. */
876 uint64_t xcp0_dis : 1; /**< [ 2: 2](SR/W) XCP0 disable. As with [SEC_DIS], but for accesses initiated by XCP0 (SCP). */
877 uint64_t xcp1_dis : 1; /**< [ 3: 3](SR/W) XCP1 disable. As with [SEC_DIS], but for accesses initiated by XCP1 (MCP). */
878 uint64_t reserved_4_6 : 3;
879 uint64_t kill : 1; /**< [ 7: 7](SR/W1S) Kill the device. Once written with one, stays
880 set until warm chip reset. If set, no access
881 allowed by any initiator. */
882 uint64_t reserved_8_63 : 56;
883 #endif /* Word 0 - End */
884 } s;
885 /* struct bdk_ecamx_domx_rslx_permit_s cn; */
886 };
887 typedef union bdk_ecamx_domx_rslx_permit bdk_ecamx_domx_rslx_permit_t;
888
889 static inline uint64_t BDK_ECAMX_DOMX_RSLX_PERMIT(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_ECAMX_DOMX_RSLX_PERMIT(unsigned long a,unsigned long b,unsigned long c)890 static inline uint64_t BDK_ECAMX_DOMX_RSLX_PERMIT(unsigned long a, unsigned long b, unsigned long c)
891 {
892 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a==0) && ((b==0) || (b==1) || (b==2)) && (c<=255)))
893 return 0x87e048060000ll + 0x1000000ll * ((a) & 0x0) + 0x800ll * ((b) & 0x3) + 8ll * ((c) & 0xff);
894 __bdk_csr_fatal("ECAMX_DOMX_RSLX_PERMIT", 3, a, b, c, 0);
895 }
896
897 #define typedef_BDK_ECAMX_DOMX_RSLX_PERMIT(a,b,c) bdk_ecamx_domx_rslx_permit_t
898 #define bustype_BDK_ECAMX_DOMX_RSLX_PERMIT(a,b,c) BDK_CSR_TYPE_RSL
899 #define basename_BDK_ECAMX_DOMX_RSLX_PERMIT(a,b,c) "ECAMX_DOMX_RSLX_PERMIT"
900 #define device_bar_BDK_ECAMX_DOMX_RSLX_PERMIT(a,b,c) 0x0 /* PF_BAR0 */
901 #define busnum_BDK_ECAMX_DOMX_RSLX_PERMIT(a,b,c) (a)
902 #define arguments_BDK_ECAMX_DOMX_RSLX_PERMIT(a,b,c) (a),(b),(c),-1
903
904 /**
905 * Register (RSL) ecam#_nop_of
906 *
907 * ECAM No-Operation Ones Faulting Register
908 */
909 union bdk_ecamx_nop_of
910 {
911 uint64_t u;
912 struct bdk_ecamx_nop_of_s
913 {
914 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
915 uint64_t ones : 64; /**< [ 63: 0](RO) Used internally to handle disabled read/write transactions. */
916 #else /* Word 0 - Little Endian */
917 uint64_t ones : 64; /**< [ 63: 0](RO) Used internally to handle disabled read/write transactions. */
918 #endif /* Word 0 - End */
919 } s;
920 /* struct bdk_ecamx_nop_of_s cn; */
921 };
922 typedef union bdk_ecamx_nop_of bdk_ecamx_nop_of_t;
923
924 static inline uint64_t BDK_ECAMX_NOP_OF(unsigned long a) __attribute__ ((pure, always_inline));
BDK_ECAMX_NOP_OF(unsigned long a)925 static inline uint64_t BDK_ECAMX_NOP_OF(unsigned long a)
926 {
927 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
928 return 0x87e048000000ll + 0x1000000ll * ((a) & 0x0);
929 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
930 return 0x87e048000000ll + 0x1000000ll * ((a) & 0x1);
931 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
932 return 0x87e048000000ll + 0x1000000ll * ((a) & 0x3);
933 __bdk_csr_fatal("ECAMX_NOP_OF", 1, a, 0, 0, 0);
934 }
935
936 #define typedef_BDK_ECAMX_NOP_OF(a) bdk_ecamx_nop_of_t
937 #define bustype_BDK_ECAMX_NOP_OF(a) BDK_CSR_TYPE_RSL
938 #define basename_BDK_ECAMX_NOP_OF(a) "ECAMX_NOP_OF"
939 #define device_bar_BDK_ECAMX_NOP_OF(a) 0x0 /* PF_BAR0 */
940 #define busnum_BDK_ECAMX_NOP_OF(a) (a)
941 #define arguments_BDK_ECAMX_NOP_OF(a) (a),-1,-1,-1
942
943 /**
944 * Register (RSL) ecam#_nop_onf
945 *
946 * ECAM No-Operation Ones Non-Faulting Register
947 */
948 union bdk_ecamx_nop_onf
949 {
950 uint64_t u;
951 struct bdk_ecamx_nop_onf_s
952 {
953 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
954 uint64_t ones : 64; /**< [ 63: 0](RO) Used internally to handle disabled read/write transactions. */
955 #else /* Word 0 - Little Endian */
956 uint64_t ones : 64; /**< [ 63: 0](RO) Used internally to handle disabled read/write transactions. */
957 #endif /* Word 0 - End */
958 } s;
959 /* struct bdk_ecamx_nop_onf_s cn; */
960 };
961 typedef union bdk_ecamx_nop_onf bdk_ecamx_nop_onf_t;
962
963 static inline uint64_t BDK_ECAMX_NOP_ONF(unsigned long a) __attribute__ ((pure, always_inline));
BDK_ECAMX_NOP_ONF(unsigned long a)964 static inline uint64_t BDK_ECAMX_NOP_ONF(unsigned long a)
965 {
966 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
967 return 0x87e048000080ll + 0x1000000ll * ((a) & 0x0);
968 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
969 return 0x87e048000080ll + 0x1000000ll * ((a) & 0x1);
970 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
971 return 0x87e048000080ll + 0x1000000ll * ((a) & 0x3);
972 __bdk_csr_fatal("ECAMX_NOP_ONF", 1, a, 0, 0, 0);
973 }
974
975 #define typedef_BDK_ECAMX_NOP_ONF(a) bdk_ecamx_nop_onf_t
976 #define bustype_BDK_ECAMX_NOP_ONF(a) BDK_CSR_TYPE_RSL
977 #define basename_BDK_ECAMX_NOP_ONF(a) "ECAMX_NOP_ONF"
978 #define device_bar_BDK_ECAMX_NOP_ONF(a) 0x0 /* PF_BAR0 */
979 #define busnum_BDK_ECAMX_NOP_ONF(a) (a)
980 #define arguments_BDK_ECAMX_NOP_ONF(a) (a),-1,-1,-1
981
982 /**
983 * Register (RSL) ecam#_nop_zf
984 *
985 * ECAM No-Operation Zero Faulting Register
986 */
987 union bdk_ecamx_nop_zf
988 {
989 uint64_t u;
990 struct bdk_ecamx_nop_zf_s
991 {
992 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
993 uint64_t zeros : 64; /**< [ 63: 0](RO) Used internally to handle disabled read/write transactions. */
994 #else /* Word 0 - Little Endian */
995 uint64_t zeros : 64; /**< [ 63: 0](RO) Used internally to handle disabled read/write transactions. */
996 #endif /* Word 0 - End */
997 } s;
998 /* struct bdk_ecamx_nop_zf_s cn; */
999 };
1000 typedef union bdk_ecamx_nop_zf bdk_ecamx_nop_zf_t;
1001
1002 static inline uint64_t BDK_ECAMX_NOP_ZF(unsigned long a) __attribute__ ((pure, always_inline));
BDK_ECAMX_NOP_ZF(unsigned long a)1003 static inline uint64_t BDK_ECAMX_NOP_ZF(unsigned long a)
1004 {
1005 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
1006 return 0x87e048000100ll + 0x1000000ll * ((a) & 0x0);
1007 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
1008 return 0x87e048000100ll + 0x1000000ll * ((a) & 0x1);
1009 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
1010 return 0x87e048000100ll + 0x1000000ll * ((a) & 0x3);
1011 __bdk_csr_fatal("ECAMX_NOP_ZF", 1, a, 0, 0, 0);
1012 }
1013
1014 #define typedef_BDK_ECAMX_NOP_ZF(a) bdk_ecamx_nop_zf_t
1015 #define bustype_BDK_ECAMX_NOP_ZF(a) BDK_CSR_TYPE_RSL
1016 #define basename_BDK_ECAMX_NOP_ZF(a) "ECAMX_NOP_ZF"
1017 #define device_bar_BDK_ECAMX_NOP_ZF(a) 0x0 /* PF_BAR0 */
1018 #define busnum_BDK_ECAMX_NOP_ZF(a) (a)
1019 #define arguments_BDK_ECAMX_NOP_ZF(a) (a),-1,-1,-1
1020
1021 /**
1022 * Register (RSL) ecam#_nop_znf
1023 *
1024 * ECAM No-Operation Zero Non-Faulting Register
1025 */
1026 union bdk_ecamx_nop_znf
1027 {
1028 uint64_t u;
1029 struct bdk_ecamx_nop_znf_s
1030 {
1031 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1032 uint64_t zeros : 64; /**< [ 63: 0](RO) Used internally to handle disabled read/write transactions. */
1033 #else /* Word 0 - Little Endian */
1034 uint64_t zeros : 64; /**< [ 63: 0](RO) Used internally to handle disabled read/write transactions. */
1035 #endif /* Word 0 - End */
1036 } s;
1037 /* struct bdk_ecamx_nop_znf_s cn; */
1038 };
1039 typedef union bdk_ecamx_nop_znf bdk_ecamx_nop_znf_t;
1040
1041 static inline uint64_t BDK_ECAMX_NOP_ZNF(unsigned long a) __attribute__ ((pure, always_inline));
BDK_ECAMX_NOP_ZNF(unsigned long a)1042 static inline uint64_t BDK_ECAMX_NOP_ZNF(unsigned long a)
1043 {
1044 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
1045 return 0x87e048000180ll + 0x1000000ll * ((a) & 0x0);
1046 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
1047 return 0x87e048000180ll + 0x1000000ll * ((a) & 0x1);
1048 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
1049 return 0x87e048000180ll + 0x1000000ll * ((a) & 0x3);
1050 __bdk_csr_fatal("ECAMX_NOP_ZNF", 1, a, 0, 0, 0);
1051 }
1052
1053 #define typedef_BDK_ECAMX_NOP_ZNF(a) bdk_ecamx_nop_znf_t
1054 #define bustype_BDK_ECAMX_NOP_ZNF(a) BDK_CSR_TYPE_RSL
1055 #define basename_BDK_ECAMX_NOP_ZNF(a) "ECAMX_NOP_ZNF"
1056 #define device_bar_BDK_ECAMX_NOP_ZNF(a) 0x0 /* PF_BAR0 */
1057 #define busnum_BDK_ECAMX_NOP_ZNF(a) (a)
1058 #define arguments_BDK_ECAMX_NOP_ZNF(a) (a),-1,-1,-1
1059
1060 /**
1061 * Register (RSL) ecam#_rsl#_nsdis
1062 *
1063 * ECAM RSL Function Nonsecure Disable Registers
1064 * This register is only implemented for ECAM0 which sources RSL.
1065 */
1066 union bdk_ecamx_rslx_nsdis
1067 {
1068 uint64_t u;
1069 struct bdk_ecamx_rslx_nsdis_s
1070 {
1071 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1072 uint64_t reserved_1_63 : 63;
1073 uint64_t dis : 1; /**< [ 0: 0](R/W) Disable ECAM RSL function in nonsecure mode. If set, the specified RSL function number
1074 (under ECAM 0 bus 1) is RAO/WI when accessed via the ECAM space with nonsecure
1075 transactions. Note this affects only ECAM configuration access, not normal I/O mapped
1076 memory accesses to the device. */
1077 #else /* Word 0 - Little Endian */
1078 uint64_t dis : 1; /**< [ 0: 0](R/W) Disable ECAM RSL function in nonsecure mode. If set, the specified RSL function number
1079 (under ECAM 0 bus 1) is RAO/WI when accessed via the ECAM space with nonsecure
1080 transactions. Note this affects only ECAM configuration access, not normal I/O mapped
1081 memory accesses to the device. */
1082 uint64_t reserved_1_63 : 63;
1083 #endif /* Word 0 - End */
1084 } s;
1085 /* struct bdk_ecamx_rslx_nsdis_s cn; */
1086 };
1087 typedef union bdk_ecamx_rslx_nsdis bdk_ecamx_rslx_nsdis_t;
1088
1089 static inline uint64_t BDK_ECAMX_RSLX_NSDIS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_RSLX_NSDIS(unsigned long a,unsigned long b)1090 static inline uint64_t BDK_ECAMX_RSLX_NSDIS(unsigned long a, unsigned long b)
1091 {
1092 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=255)))
1093 return 0x87e048050000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0xff);
1094 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=255)))
1095 return 0x87e048050000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
1096 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=255)))
1097 return 0x87e048050000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0xff);
1098 __bdk_csr_fatal("ECAMX_RSLX_NSDIS", 2, a, b, 0, 0);
1099 }
1100
1101 #define typedef_BDK_ECAMX_RSLX_NSDIS(a,b) bdk_ecamx_rslx_nsdis_t
1102 #define bustype_BDK_ECAMX_RSLX_NSDIS(a,b) BDK_CSR_TYPE_RSL
1103 #define basename_BDK_ECAMX_RSLX_NSDIS(a,b) "ECAMX_RSLX_NSDIS"
1104 #define device_bar_BDK_ECAMX_RSLX_NSDIS(a,b) 0x0 /* PF_BAR0 */
1105 #define busnum_BDK_ECAMX_RSLX_NSDIS(a,b) (a)
1106 #define arguments_BDK_ECAMX_RSLX_NSDIS(a,b) (a),(b),-1,-1
1107
1108 /**
1109 * Register (RSL) ecam#_rsl#_sdis
1110 *
1111 * ECAM RSL Function Secure Disable Registers
1112 * This register is only implemented for ECAM0 which sources RSL.
1113 */
1114 union bdk_ecamx_rslx_sdis
1115 {
1116 uint64_t u;
1117 struct bdk_ecamx_rslx_sdis_s
1118 {
1119 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1120 uint64_t reserved_2_63 : 62;
1121 uint64_t sec : 1; /**< [ 1: 1](SR/W) Secure ECAM RSL function. If set, the indexed RSL function number (under ECAM 0
1122 bus 1) is secured and RAO/WI when accessed via the ECAM space with nonsecure
1123 transactions. This bit overrides ECAM()_RSL()_NSDIS[DIS]. */
1124 uint64_t dis : 1; /**< [ 0: 0](SR/W) Disable ECAM RSL function in secure mode. If set, ECAM secure read/write operations to the
1125 indexed
1126 RSL function number (under ECAM 0 bus 1) are RAO/WI when accessed via the ECAM
1127 space. This bit is similar to the nonsecure ECAM()_RSL()_NSDIS[DIS]. */
1128 #else /* Word 0 - Little Endian */
1129 uint64_t dis : 1; /**< [ 0: 0](SR/W) Disable ECAM RSL function in secure mode. If set, ECAM secure read/write operations to the
1130 indexed
1131 RSL function number (under ECAM 0 bus 1) are RAO/WI when accessed via the ECAM
1132 space. This bit is similar to the nonsecure ECAM()_RSL()_NSDIS[DIS]. */
1133 uint64_t sec : 1; /**< [ 1: 1](SR/W) Secure ECAM RSL function. If set, the indexed RSL function number (under ECAM 0
1134 bus 1) is secured and RAO/WI when accessed via the ECAM space with nonsecure
1135 transactions. This bit overrides ECAM()_RSL()_NSDIS[DIS]. */
1136 uint64_t reserved_2_63 : 62;
1137 #endif /* Word 0 - End */
1138 } s;
1139 /* struct bdk_ecamx_rslx_sdis_s cn; */
1140 };
1141 typedef union bdk_ecamx_rslx_sdis bdk_ecamx_rslx_sdis_t;
1142
1143 static inline uint64_t BDK_ECAMX_RSLX_SDIS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_RSLX_SDIS(unsigned long a,unsigned long b)1144 static inline uint64_t BDK_ECAMX_RSLX_SDIS(unsigned long a, unsigned long b)
1145 {
1146 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=255)))
1147 return 0x87e048040000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0xff);
1148 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=255)))
1149 return 0x87e048040000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
1150 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=255)))
1151 return 0x87e048040000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0xff);
1152 __bdk_csr_fatal("ECAMX_RSLX_SDIS", 2, a, b, 0, 0);
1153 }
1154
1155 #define typedef_BDK_ECAMX_RSLX_SDIS(a,b) bdk_ecamx_rslx_sdis_t
1156 #define bustype_BDK_ECAMX_RSLX_SDIS(a,b) BDK_CSR_TYPE_RSL
1157 #define basename_BDK_ECAMX_RSLX_SDIS(a,b) "ECAMX_RSLX_SDIS"
1158 #define device_bar_BDK_ECAMX_RSLX_SDIS(a,b) 0x0 /* PF_BAR0 */
1159 #define busnum_BDK_ECAMX_RSLX_SDIS(a,b) (a)
1160 #define arguments_BDK_ECAMX_RSLX_SDIS(a,b) (a),(b),-1,-1
1161
1162 /**
1163 * Register (RSL) ecam#_rsl#_skill
1164 *
1165 * ECAM RSL Function Secure Disable Registers
1166 * This register is only implemented for ECAM0 which sources RSL.
1167 */
1168 union bdk_ecamx_rslx_skill
1169 {
1170 uint64_t u;
1171 struct bdk_ecamx_rslx_skill_s
1172 {
1173 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1174 uint64_t reserved_1_63 : 63;
1175 uint64_t skill : 1; /**< [ 0: 0](SR/W1S) ECAM function kill.
1176 Write one to set. Once set, cannot be cleared until soft reset. If set,
1177 the indexed ECAM bus/function/device number is RAO/WI when accessed via
1178 the ECAM space with any (secure/nonsecure) transactions. */
1179 #else /* Word 0 - Little Endian */
1180 uint64_t skill : 1; /**< [ 0: 0](SR/W1S) ECAM function kill.
1181 Write one to set. Once set, cannot be cleared until soft reset. If set,
1182 the indexed ECAM bus/function/device number is RAO/WI when accessed via
1183 the ECAM space with any (secure/nonsecure) transactions. */
1184 uint64_t reserved_1_63 : 63;
1185 #endif /* Word 0 - End */
1186 } s;
1187 /* struct bdk_ecamx_rslx_skill_s cn; */
1188 };
1189 typedef union bdk_ecamx_rslx_skill bdk_ecamx_rslx_skill_t;
1190
1191 static inline uint64_t BDK_ECAMX_RSLX_SKILL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_ECAMX_RSLX_SKILL(unsigned long a,unsigned long b)1192 static inline uint64_t BDK_ECAMX_RSLX_SKILL(unsigned long a, unsigned long b)
1193 {
1194 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=255)))
1195 return 0x87e048090000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0xff);
1196 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=255)))
1197 return 0x87e048090000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0xff);
1198 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && ((a<=3) && (b<=255)))
1199 return 0x87e048090000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0xff);
1200 __bdk_csr_fatal("ECAMX_RSLX_SKILL", 2, a, b, 0, 0);
1201 }
1202
1203 #define typedef_BDK_ECAMX_RSLX_SKILL(a,b) bdk_ecamx_rslx_skill_t
1204 #define bustype_BDK_ECAMX_RSLX_SKILL(a,b) BDK_CSR_TYPE_RSL
1205 #define basename_BDK_ECAMX_RSLX_SKILL(a,b) "ECAMX_RSLX_SKILL"
1206 #define device_bar_BDK_ECAMX_RSLX_SKILL(a,b) 0x0 /* PF_BAR0 */
1207 #define busnum_BDK_ECAMX_RSLX_SKILL(a,b) (a)
1208 #define arguments_BDK_ECAMX_RSLX_SKILL(a,b) (a),(b),-1,-1
1209
1210 /**
1211 * Register (RSL) ecam#_scratch
1212 *
1213 * INTERNAL: ECAM Scratch Register
1214 */
1215 union bdk_ecamx_scratch
1216 {
1217 uint64_t u;
1218 struct bdk_ecamx_scratch_s
1219 {
1220 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1221 uint64_t data : 64; /**< [ 63: 0](R/W) Test register for CSR access. */
1222 #else /* Word 0 - Little Endian */
1223 uint64_t data : 64; /**< [ 63: 0](R/W) Test register for CSR access. */
1224 #endif /* Word 0 - End */
1225 } s;
1226 /* struct bdk_ecamx_scratch_s cn; */
1227 };
1228 typedef union bdk_ecamx_scratch bdk_ecamx_scratch_t;
1229
1230 static inline uint64_t BDK_ECAMX_SCRATCH(unsigned long a) __attribute__ ((pure, always_inline));
BDK_ECAMX_SCRATCH(unsigned long a)1231 static inline uint64_t BDK_ECAMX_SCRATCH(unsigned long a)
1232 {
1233 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a==0))
1234 return 0x87e048080000ll + 0x1000000ll * ((a) & 0x0);
1235 __bdk_csr_fatal("ECAMX_SCRATCH", 1, a, 0, 0, 0);
1236 }
1237
1238 #define typedef_BDK_ECAMX_SCRATCH(a) bdk_ecamx_scratch_t
1239 #define bustype_BDK_ECAMX_SCRATCH(a) BDK_CSR_TYPE_RSL
1240 #define basename_BDK_ECAMX_SCRATCH(a) "ECAMX_SCRATCH"
1241 #define device_bar_BDK_ECAMX_SCRATCH(a) 0x0 /* PF_BAR0 */
1242 #define busnum_BDK_ECAMX_SCRATCH(a) (a)
1243 #define arguments_BDK_ECAMX_SCRATCH(a) (a),-1,-1,-1
1244
1245 #endif /* __BDK_CSRS_ECAM_H__ */
1246