1 /*
2  * Copyright (c) 2023, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef APUSYS_POWER_H
8 #define APUSYS_POWER_H
9 
10 #include <platform_def.h>
11 
12 enum APU_CLKSRC_ID {
13 	PLL_CONN = 0, /* MNOC */
14 	PLL_UP,
15 	PLL_VPU,
16 	PLL_DLA,
17 	PLL_NUM,
18 };
19 
20 enum APU_ARE_ID {
21 	APU_ARE0 = 0,
22 	APU_ARE1,
23 	APU_ARE2,
24 	APU_ARE_NUM,
25 };
26 
27 enum APU_D4_SLV_CTRL {
28 	D4_SLV_OFF = 0,
29 	D4_SLV_ON,
30 };
31 
32 enum APU_BACKUP_RESTORE_CTRL {
33 	APU_CTRL_BACKUP		= 0,
34 	APU_CTRL_RESTORE	= 1,
35 };
36 
37 struct apu_restore_data {
38 	uint32_t reg;
39 	uint32_t data;
40 };
41 
42 #define APU_POLL_STEP_US			(5)
43 
44 #define OUT_CLK_FREQ_MIN			(1500)
45 #define BASIC_CLK_FREQ				(26)
46 #define DDS_SHIFT				(14)
47 
48 #define APUPLL0_DEFAULT_FREQ			(900)
49 #define APUPLL1_DEFAULT_FREQ			(832)
50 #define APUPLL2_DEFAULT_FREQ			(700)
51 #define APUPLL3_DEFAULT_FREQ			(700)
52 
53 #define APU_TOP_ON_POLLING_TIMEOUT_US		(10000)
54 #define APU_TOP_OFF_POLLING_TIMEOUT_US		(5 * APU_TOP_ON_POLLING_TIMEOUT_US)
55 #define APU_ARE_POLLING_TIMEOUT_US		(10000)
56 
57 /* APU related reg */
58 #define APU_VCORE_BASE				(APU_RCX_VCORE_CONFIG)
59 #define APU_RCX_BASE				(APU_RCX_CONFIG)
60 #define APU_RPC_BASE				(APU_RPCTOP)
61 #define APU_PCU_BASE				(APU_PCUTOP)
62 #define APU_ARE0_BASE				(APU_ARETOP_ARE0)
63 #define APU_ARE1_BASE				(APU_ARETOP_ARE1)
64 #define APU_ARE2_BASE				(APU_ARETOP_ARE2)
65 #define APU_MBOX0_BASE				(APU_MBOX0)
66 #define APU_AO_CTL_BASE				(APU_AO_CTRL)
67 #define APU_PLL_BASE				(APU_PLL)
68 #define APU_ACC_BASE				(APU_ACC)
69 #define APU_ACX0_RPC_LITE_BASE			(APU_ACX0_RPC_LITE)
70 
71 /* RPC offset define */
72 #define APU_RPC_TOP_CON				(0x0000)
73 #define APU_RPC_TOP_SEL				(0x0004)
74 #define APU_RPC_STATUS				(0x0014)
75 #define APU_RPC_TOP_SEL_1			(0x0018)
76 #define APU_RPC_HW_CON				(0x001c)
77 #define APU_RPC_INTF_PWR_RDY			(0x0044)
78 #define APU_RPC_SW_TYPE0			(0x0200)
79 
80 /* RPC control */
81 #define SRAM_AOC_ISO_CLR			BIT(7)
82 #define BUCK_ELS_EN_SET				BIT(10)
83 #define BUCK_ELS_EN_CLR				BIT(11)
84 #define BUCK_AO_RST_B_SET			BIT(12)
85 #define BUCK_AO_RST_B_CLR			BIT(13)
86 #define BUCK_PROT_REQ_SET			BIT(14)
87 #define BUCK_PROT_REQ_CLR			BIT(15)
88 #define SW_TYPE					BIT(1)
89 #define RPC_CTRL				(0x0000009e)
90 #define RPC_TOP_CTRL				(0x0800501e)
91 #define RPC_TOP_CTRL1				BIT(20)
92 #define AFC_ENA					BIT(16)
93 #define REG_WAKEUP_SET				BIT(8)
94 #define REG_WAKEUP_CLR				BIT(12)
95 #define PWR_RDY					BIT(0)
96 #define PWR_OFF					(0)
97 #define RPC_STATUS_RDY				BIT(29)
98 #define RSV10					BIT(10)
99 #define CLR_IRQ					(0x6)
100 #define SLEEP_REQ				BIT(0)
101 
102 /* PLL offset define */
103 #define PLL4H_PLL1_CON1				(0x000c)
104 #define PLL4H_PLL2_CON1				(0x001c)
105 #define PLL4H_PLL3_CON1				(0x002c)
106 #define PLL4H_PLL4_CON1				(0x003c)
107 #define PLL4HPLL_FHCTL_HP_EN			(0x0e00)
108 #define PLL4HPLL_FHCTL_CLK_CON			(0x0e08)
109 #define PLL4HPLL_FHCTL_RST_CON			(0x0e0c)
110 #define PLL4HPLL_FHCTL0_CFG			(0x0e3c)
111 #define PLL4HPLL_FHCTL0_DDS			(0x0e44)
112 #define PLL4HPLL_FHCTL1_CFG			(0x0e50)
113 #define PLL4HPLL_FHCTL1_DDS			(0x0e58)
114 #define PLL4HPLL_FHCTL2_CFG			(0x0e64)
115 #define PLL4HPLL_FHCTL2_DDS			(0x0e6c)
116 #define PLL4HPLL_FHCTL3_CFG			(0x0e78)
117 #define PLL4HPLL_FHCTL3_DDS			(0x0e80)
118 
119 /* PLL control */
120 #define PLL4H_PLL_HP_EN				(0xf)
121 #define PLL4H_PLL_HP_CLKEN			(0xf)
122 #define PLL4H_PLL_HP_SWRSTB			(0xf)
123 #define FHCTL0_EN				BIT(0)
124 #define	SFSTR0_EN				BIT(2)
125 #define RG_PLL_POSDIV_MASK			(0x7)
126 #define RG_PLL_POSDIV_SFT			(24)
127 #define FHCTL_PLL_TGL_ORG			BIT(31)
128 
129 /* ACC offset define */
130 #define APU_ACC_CONFG_SET0			(0x0000)
131 #define APU_ACC_CONFG_SET1			(0x0004)
132 #define APU_ACC_CONFG_SET2			(0x0008)
133 #define APU_ACC_CONFG_SET3			(0x000c)
134 #define APU_ACC_CONFG_CLR0			(0x0040)
135 #define APU_ACC_CONFG_CLR1			(0x0044)
136 #define APU_ACC_CONFG_CLR2			(0x0048)
137 #define APU_ACC_CONFG_CLR3			(0x004c)
138 #define APU_ACC_CLK_INV_EN_SET			(0x00e8)
139 #define APU_ACC_AUTO_CTRL_SET2			(0x0128)
140 #define APU_ACC_AUTO_CTRL_SET3			(0x012c)
141 
142 /* ACC control */
143 #define CGEN_SOC				BIT(2)
144 #define HW_CTRL_EN				BIT(15)
145 #define CLK_REQ_SW_EN				BIT(8)
146 #define CLK_INV_EN				(0xaaa8)
147 
148 /* ARE offset define */
149 #define APU_ARE_INI_CTRL			(0x0000)
150 #define APU_ARE_GLO_FSM				(0x0048)
151 #define APU_ARE_ENTRY0_SRAM_H			(0x0c00)
152 #define APU_ARE_ENTRY0_SRAM_L			(0x0800)
153 #define APU_ARE_ENTRY1_SRAM_H			(0x0c04)
154 #define APU_ARE_ENTRY1_SRAM_L			(0x0804)
155 #define APU_ARE_ENTRY2_SRAM_H			(0x0c08)
156 #define APU_ARE_ENTRY2_SRAM_L			(0x0808)
157 
158 /* ARE control */
159 #define ARE_ENTRY_CFG_H				(0x00140000)
160 #define ARE0_ENTRY2_CFG_L			(0x004e0804)
161 #define ARE1_ENTRY2_CFG_L			(0x004e0806)
162 #define ARE2_ENTRY2_CFG_L			(0x004e0807)
163 #define ARE_GLO_FSM_IDLE			BIT(0)
164 #define ARE_ENTRY0_SRAM_H_INIT			(0x12345678)
165 #define ARE_ENTRY0_SRAM_L_INIT			(0x89abcdef)
166 #define ARE_ENTRY1_SRAM_H_INIT			(0xfedcba98)
167 #define ARE_ENTRY1_SRAM_L_INIT			(0x76543210)
168 #define ARE_CONFG_INI				BIT(2)
169 
170 /* VCORE offset define */
171 #define APUSYS_VCORE_CG_CLR			(0x0008)
172 
173 /* RCX offset define */
174 #define APU_RCX_CG_CLR				(0x0008)
175 
176 /* SPM offset define */
177 #define APUSYS_BUCK_ISOLATION			(0x03ec)
178 
179 /* SPM control*/
180 #define IPU_EXT_BUCK_ISO			(0x21)
181 
182 /* apu_rcx_ao_ctrl  */
183 #define CSR_DUMMY_0_ADDR			(0x0024)
184 
185 /* apu_rcx_ao_ctrl control */
186 #define VCORE_ARE_REQ				BIT(2)
187 
188 /* xpu2apusys */
189 #define INFRA_FMEM_BUS_u_SI21_CTRL_0		(0x002c)
190 #define INFRA_FMEM_BUS_u_SI22_CTRL_0		(0x0044)
191 #define INFRA_FMEM_BUS_u_SI11_CTRL_0		(0x0048)
192 #define INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_0	(0x01d0)
193 
194 /* xpu2apusys */
195 #define INFRA_FMEM_BUS_u_SI21_CTRL_EN		BIT(12)
196 #define INFRA_FMEM_BUS_u_SI22_CTRL_EN		BIT(13)
197 #define INFRA_FMEM_BUS_u_SI11_CTRL_EN		BIT(11)
198 #define INFRA_FMEM_M6M7_BUS_u_SI24_CTRL_EN	BIT(15)
199 
200 /* PCU offset define */
201 #define APU_PCU_CTRL_SET			(0x0000)
202 #define APU_PCU_BUCK_STEP_SEL			(0x0030)
203 #define APU_PCU_BUCK_ON_DAT0_L			(0x0080)
204 #define APU_PCU_BUCK_ON_DAT0_H			(0x0084)
205 #define APU_PCU_BUCK_ON_DAT1_L			(0x0088)
206 #define APU_PCU_BUCK_ON_DAT1_H			(0x008c)
207 #define APU_PCU_BUCK_OFF_DAT0_L			(0x00a0)
208 #define APU_PCU_BUCK_OFF_DAT0_H			(0x00a4)
209 #define APU_PCU_BUCK_OFF_DAT1_L			(0x00a8)
210 #define APU_PCU_BUCK_OFF_DAT1_H			(0x00ac)
211 #define APU_PCU_BUCK_ON_SLE0			(0x00c0)
212 #define APU_PCU_BUCK_ON_SLE1			(0x00c4)
213 #define APU_PCU_BUCK_ON_SETTLE_TIME		(0x012c)
214 
215 /* PCU initial data */
216 #define MT6359P_RG_BUCK_VMODEM_EN_ADDR		(0x1688)
217 #define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR		(0x1f2e)
218 #define BUCK_VAPU_PMIC_REG_EN_ADDR		MT6359P_RG_BUCK_VMODEM_EN_ADDR
219 #define BUCK_VAPU_SRAM_PMIC_REG_EN_ADDR		MT6359P_RG_LDO_VSRAM_MD_EN_ADDR
220 
221 /* PCU control */
222 #define AUTO_BUCK_EN				BIT(16)
223 #define BUCK_ON_OFF_CMD_EN			(0x33)
224 #define BUCK_OFFSET_SFT				(16)
225 #define BUCK_ON_CMD				(0x1)
226 #define BUCK_OFF_CMD				(0x0)
227 #define CMD_OP					(0x4)
228 
229 /* RPC lite offset define */
230 #define APU_RPC_SW_TYPE2			(0x0208)
231 #define APU_RPC_SW_TYPE3			(0x020c)
232 #define APU_RPC_SW_TYPE4			(0x0210)
233 #define APU_RPC_SW_TYPE5			(0x0214)
234 #define APU_RPC_SW_TYPE6			(0x0218)
235 #define APU_RPC_SW_TYPE7			(0x021c)
236 #define APU_RPC_SW_TYPE8			(0x0220)
237 #define APU_RPC_SW_TYPE9			(0x0224)
238 
239 /* power flow sync */
240 #define PWR_FLOW_SYNC_REG			(0x0440)
241 
242 #define CG_CLR					(0xffffffff)
243 
244 int apusys_power_init(void);
245 int apusys_kernel_apusys_pwr_top_on(void);
246 int apusys_kernel_apusys_pwr_top_off(void);
247 
248 #endif /* APUSYS_POWER_H */
249