1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <edid.h> 4 #include <types.h> 5 6 #ifndef __ANX7625_H__ 7 #define __ANX7625_H__ 8 9 #ifndef LOG_TAG 10 #define LOG_TAG "anx7625dp" 11 #endif 12 13 #define ANX7625_DRV_VERSION "0.1.04" 14 15 /* Loading OCM re-trying times */ 16 #define OCM_LOADING_TIME 10 17 18 /********* ANX7625 Register **********/ 19 #define ANXI2CSIM 20 #ifdef ANXI2CSIM 21 #define TX_P0_ADDR 0x38 22 #define TX_P1_ADDR 0x3D 23 #define TX_P2_ADDR 0x39 24 #define RX_P0_ADDR 0x3F 25 #define RX_P1_ADDR 0x42 26 #define RX_P2_ADDR 0x2A 27 #define TCPC_INTERFACE_ADDR 0x2C 28 #else 29 #define TX_P0_ADDR 0x70 30 #define TX_P1_ADDR 0x7A 31 #define TX_P2_ADDR 0x72 32 #define RX_P0_ADDR 0x7e 33 #define RX_P1_ADDR 0x84 34 #define RX_P2_ADDR 0x54 35 #define TCPC_INTERFACE_ADDR 0x58 36 #endif 37 38 #define RSVD_00_ADDR 0x00 39 #define RSVD_D1_ADDR 0xD1 40 #define RSVD_60_ADDR 0x60 41 #define RSVD_39_ADDR 0x39 42 #define RSVD_7F_ADDR 0x7F 43 44 /* anx7625 clock frequency in Hz */ 45 #define XTAL_FRQ (27*1000000) 46 47 #define POST_DIVIDER_MIN 1 48 #define POST_DIVIDER_MAX 16 49 #define PLL_OUT_FREQ_MIN 520000000UL 50 #define PLL_OUT_FREQ_MAX 730000000UL 51 #define PLL_OUT_FREQ_ABS_MIN 300000000UL 52 #define PLL_OUT_FREQ_ABS_MAX 800000000UL 53 #define MAX_UNSIGNED_24BIT 16777215UL 54 55 /***************************************************************/ 56 /* Register definition of device address 0x58 */ 57 58 #define PRODUCT_ID_L 0x02 59 #define PRODUCT_ID_H 0x03 60 61 #define INTR_ALERT_1 0xCC 62 #define INTR_SOFTWARE_INT (1<<3) 63 #define INTR_RECEIVED_MSG (1<<5) 64 65 #define SYSTEM_STSTUS 0x45 66 #define INTERFACE_CHANGE_INT 0x44 67 #define HPD_STATUS_CHANGE 0x80 68 #define HPD_STATUS 0x80 69 70 /******** END of I2C Address 0x58 ********/ 71 72 /***************************************************************/ 73 /* Register definition of device address 0x70 */ 74 #define I2C_ADDR_70_DPTX 0x70 75 76 #define SP_TX_LINK_BW_SET_REG 0xA0 77 #define SP_TX_LANE_COUNT_SET_REG 0xA1 78 79 #define M_VID_0 0xC0 80 #define M_VID_1 0xC1 81 #define M_VID_2 0xC2 82 #define N_VID_0 0xC3 83 #define N_VID_1 0xC4 84 #define N_VID_2 0xC5 85 86 /***************************************************************/ 87 /* Register definition of device address 0x72 */ 88 #define AUX_RST 0x04 89 #define RST_CTRL2 0x07 90 91 #define SP_TX_TOTAL_LINE_STA_L 0x24 92 #define SP_TX_TOTAL_LINE_STA_H 0x25 93 #define SP_TX_ACT_LINE_STA_L 0x26 94 #define SP_TX_ACT_LINE_STA_H 0x27 95 #define SP_TX_V_F_PORCH_STA 0x28 96 #define SP_TX_V_SYNC_STA 0x29 97 #define SP_TX_V_B_PORCH_STA 0x2A 98 #define SP_TX_TOTAL_PIXEL_STA_L 0x2B 99 #define SP_TX_TOTAL_PIXEL_STA_H 0x2C 100 #define SP_TX_ACT_PIXEL_STA_L 0x2D 101 #define SP_TX_ACT_PIXEL_STA_H 0x2E 102 #define SP_TX_H_F_PORCH_STA_L 0x2F 103 #define SP_TX_H_F_PORCH_STA_H 0x30 104 #define SP_TX_H_SYNC_STA_L 0x31 105 #define SP_TX_H_SYNC_STA_H 0x32 106 #define SP_TX_H_B_PORCH_STA_L 0x33 107 #define SP_TX_H_B_PORCH_STA_H 0x34 108 109 #define SP_TX_VID_CTRL 0x84 110 #define SP_TX_BPC_MASK 0xE0 111 #define SP_TX_BPC_6 0x00 112 #define SP_TX_BPC_8 0x20 113 #define SP_TX_BPC_10 0x40 114 #define SP_TX_BPC_12 0x60 115 116 #define VIDEO_BIT_MATRIX_12 0x4c 117 118 #define AUDIO_CHANNEL_STATUS_1 0xd0 119 #define AUDIO_CHANNEL_STATUS_2 0xd1 120 #define AUDIO_CHANNEL_STATUS_3 0xd2 121 #define AUDIO_CHANNEL_STATUS_4 0xd3 122 #define AUDIO_CHANNEL_STATUS_5 0xd4 123 #define AUDIO_CHANNEL_STATUS_6 0xd5 124 #define TDM_SLAVE_MODE 0x10 125 #define I2S_SLAVE_MODE 0x08 126 127 #define AUDIO_CONTROL_REGISTER 0xe6 128 #define TDM_TIMING_MODE 0x08 129 130 #define I2C_ADDR_72_DPTX 0x72 131 132 #define VIDEO_CONTROL_0 0x08 133 134 #define ACTIVE_LINES_L 0x14 135 #define ACTIVE_LINES_H 0x15 /* note: bit[7:6] are reserved */ 136 #define VERTICAL_FRONT_PORCH 0x16 137 #define VERTICAL_SYNC_WIDTH 0x17 138 #define VERTICAL_BACK_PORCH 0x18 139 140 #define HORIZONTAL_TOTAL_PIXELS_L 0x19 141 #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* note: bit[7:6] are reserved */ 142 #define HORIZONTAL_ACTIVE_PIXELS_L 0x1B 143 #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* note: bit[7:6] are reserved */ 144 #define HORIZONTAL_FRONT_PORCH_L 0x1D 145 #define HORIZONTAL_FRONT_PORCH_H 0x1E /* note: bit[7:4] are reserved */ 146 #define HORIZONTAL_SYNC_WIDTH_L 0x1F 147 #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* note: bit[7:4] are reserved */ 148 #define HORIZONTAL_BACK_PORCH_L 0x21 149 #define HORIZONTAL_BACK_PORCH_H 0x22 /* note: bit[7:4] are reserved */ 150 151 /******** END of I2C Address 0x72 *********/ 152 /***************************************************************/ 153 /* Register definition of device address 0x7e */ 154 155 #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E 156 157 #define XTAL_FRQ_SEL 0x3F 158 /* bit field positions */ 159 #define XTAL_FRQ_SEL_POS 5 160 /* bit field values */ 161 #define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) 162 #define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) 163 164 #define R_DSC_CTRL_0 0x40 165 #define READ_STATUS_EN 7 166 #define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ 167 #define DSC_BIST_DONE 1 /* bit[5:1]: 1=DSC MBIST pass */ 168 #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ 169 170 #define OCM_FW_VERSION 0x31 171 #define OCM_FW_REVERSION 0x32 172 173 #define AP_AUX_ADDR_7_0 0x11 174 #define AP_AUX_ADDR_15_8 0x12 175 #define AP_AUX_ADDR_19_16 0x13 176 177 /* note: bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ 178 #define AP_AUX_CTRL_STATUS 0x14 179 #define AP_AUX_CTRL_OP_EN 0x10 180 #define AP_AUX_CTRL_ADDRONLY 0x20 181 182 #define AP_AUX_BUFF_START 0x15 183 #define PIXEL_CLOCK_L 0x25 184 #define PIXEL_CLOCK_H 0x26 185 186 #define AP_AUX_COMMAND 0x27 /* com+len */ 187 /* bit 0&1: 3D video structure */ 188 /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ 189 #define AP_AV_STATUS 0x28 190 #define AP_VIDEO_CHG (1<<2) 191 #define AP_AUDIO_CHG (1<<3) 192 #define AP_MIPI_MUTE (1<<4) /* 1:MIPI input mute, 0: unmute */ 193 #define AP_MIPI_RX_EN (1<<5) /* 1: MIPI RX input in 0: no RX in */ 194 #define AP_DISABLE_PD (1<<6) 195 #define AP_DISABLE_DISPLAY (1<<7) 196 /***************************************************************/ 197 /* Register definition of device address 0x84 */ 198 #define MIPI_PHY_CONTROL_3 0x03 199 #define MIPI_HS_PWD_CLK 7 200 #define MIPI_HS_RT_CLK 6 201 #define MIPI_PD_CLK 5 202 #define MIPI_CLK_RT_MANUAL_PD_EN 4 203 #define MIPI_CLK_HS_MANUAL_PD_EN 3 204 #define MIPI_CLK_DET_DET_BYPASS 2 205 #define MIPI_CLK_MISS_CTRL 1 206 #define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 207 208 #define MIPI_LANE_CTRL_0 0x05 209 #define MIPI_TIME_HS_PRPR 0x08 210 211 /* After MIPI RX protocol layer received this many video frames, */ 212 /* protocol layer starts to reconstruct video stream from PHY */ 213 #define MIPI_VIDEO_STABLE_CNT 0x0A 214 215 #define MIPI_LANE_CTRL_10 0x0F 216 #define MIPI_DIGITAL_ADJ_1 0x1B 217 218 #define MIPI_PLL_M_NUM_23_16 0x1E 219 #define MIPI_PLL_M_NUM_15_8 0x1F 220 #define MIPI_PLL_M_NUM_7_0 0x20 221 #define MIPI_PLL_N_NUM_23_16 0x21 222 #define MIPI_PLL_N_NUM_15_8 0x22 223 #define MIPI_PLL_N_NUM_7_0 0x23 224 225 #define MIPI_DIGITAL_PLL_6 0x2A 226 /* bit[7:6]: VCO band control, only effective */ 227 /* when MIPI_PLL_FORCE_BAND_EN (0x84:0x2B[6]) is 1 */ 228 #define MIPI_M_NUM_READY 0x10 229 #define MIPI_N_NUM_READY 0x08 230 #define STABLE_INTEGER_CNT_EN 0x04 231 #define MIPI_PLL_TEST_BIT 0 232 /* bit[1:0]: test point output select - */ 233 /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ 234 235 #define MIPI_DIGITAL_PLL_7 0x2B 236 #define MIPI_PLL_FORCE_N_EN 7 237 #define MIPI_PLL_FORCE_BAND_EN 6 238 239 #define MIPI_PLL_VCO_TUNE_REG 4 240 /* bit[5:4]: VCO metal capacitance - */ 241 /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ 242 #define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 243 244 #define MIPI_PLL_PLL_LDO_BIT 2 245 /* bit[3:2]: vco_v2i power - */ 246 /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ 247 #define MIPI_PLL_RESET_N 0x02 248 #define MIPI_FRQ_FORCE_NDET 0 249 250 #define MIPI_ALERT_CLR_0 0x2D 251 #define HS_link_error_clear 7 252 /* This bit itself is S/C, and it clears 0x84:0x31[7] */ 253 254 #define MIPI_ALERT_OUT_0 0x31 255 #define check_sum_err_hs_sync 7 256 /* This bit is cleared by 0x84:0x2D[7] */ 257 258 #define MIPI_DIGITAL_PLL_8 0x33 259 #define MIPI_POST_DIV_VAL 4 260 /* n means divided by (n+1), n = 0~15 */ 261 #define MIPI_EN_LOCK_FRZ 3 262 #define MIPI_FRQ_COUNTER_RST 2 263 #define MIPI_FRQ_SET_REG_8 1 264 /* bit 0 is reserved */ 265 266 #define MIPI_DIGITAL_PLL_9 0x34 267 268 #define MIPI_DIGITAL_PLL_16 0x3B 269 #define MIPI_FRQ_FREEZE_NDET 7 270 #define MIPI_FRQ_REG_SET_ENABLE 6 271 #define MIPI_REG_FORCE_SEL_EN 5 272 #define MIPI_REG_SEL_DIV_REG 4 273 #define MIPI_REG_FORCE_PRE_DIV_EN 3 274 /* bit 2 is reserved */ 275 #define MIPI_FREF_D_IND 1 276 #define REF_CLK_27000kHz 1 277 #define REF_CLK_19200kHz 0 278 #define MIPI_REG_PLL_PLL_TEST_ENABLE 0 279 280 #define MIPI_DIGITAL_PLL_18 0x3D 281 #define FRQ_COUNT_RB_SEL 7 282 #define REG_FORCE_POST_DIV_EN 6 283 #define MIPI_DPI_SELECT 5 284 #define SELECT_DSI 1 285 #define SELECT_DPI 0 286 #define REG_BAUD_DIV_RATIO 0 287 288 #define H_BLANK_L 0x3E 289 /* for DSC only */ 290 #define H_BLANK_H 0x3F 291 /* for DSC only; note: bit[7:6] are reserved */ 292 #define MIPI_SWAP 0x4A 293 #define MIPI_SWAP_CH0 7 294 #define MIPI_SWAP_CH1 6 295 #define MIPI_SWAP_CH2 5 296 #define MIPI_SWAP_CH3 4 297 #define MIPI_SWAP_CLK 3 298 /* bit[2:0] are reserved */ 299 300 /******** END of I2C Address 0x84 *********/ 301 302 /* DPCD regs */ 303 #define DPCD_DPCD_REV 0x00 304 #define DPCD_MAX_LINK_RATE 0x01 305 #define DPCD_MAX_LANE_COUNT 0x02 306 307 /********* ANX7625 Register End **********/ 308 309 /***************** Display *****************/ 310 enum AudioFs { 311 AUDIO_FS_441K = 0x00, 312 AUDIO_FS_48K = 0x02, 313 AUDIO_FS_32K = 0x03, 314 AUDIO_FS_882K = 0x08, 315 AUDIO_FS_96K = 0x0a, 316 AUDIO_FS_1764K = 0x0c, 317 AUDIO_FS_192K = 0x0e 318 }; 319 320 enum AudioWdLen { 321 AUDIO_W_LEN_16_20MAX = 0x02, 322 AUDIO_W_LEN_18_20MAX = 0x04, 323 AUDIO_W_LEN_17_20MAX = 0x0c, 324 AUDIO_W_LEN_19_20MAX = 0x08, 325 AUDIO_W_LEN_20_20MAX = 0x0a, 326 AUDIO_W_LEN_20_24MAX = 0x03, 327 AUDIO_W_LEN_22_24MAX = 0x05, 328 AUDIO_W_LEN_21_24MAX = 0x0d, 329 AUDIO_W_LEN_23_24MAX = 0x09, 330 AUDIO_W_LEN_24_24MAX = 0x0b 331 }; 332 333 #define I2S_CH_2 0x01 334 #define TDM_CH_4 0x03 335 #define TDM_CH_6 0x05 336 #define TDM_CH_8 0x07 337 338 #define MAX_DPCD_BUFFER_SIZE 16 339 340 #define ONE_BLOCK_SIZE 128 341 #define FOUR_BLOCK_SIZE (128*4) 342 343 struct display_timing { 344 unsigned int pixelclock; 345 unsigned int hactive; 346 unsigned int hfront_porch; 347 unsigned int hback_porch; 348 unsigned int hsync_len; 349 unsigned int vactive; 350 unsigned int vfront_porch; 351 unsigned int vback_porch; 352 unsigned int vsync_len; 353 unsigned int k_val; 354 }; 355 356 int anx7625_dp_start(uint8_t bus, const struct edid *edid); 357 int anx7625_dp_get_edid(uint8_t bus, struct edid *out); 358 int anx7625_init(uint8_t bus); 359 #endif /* __ANX7625_H__ */ 360