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A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.parmtype=disable_bypass:boolparm=disable_bypass:Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.description=IOMMU API for ARM architected SMMU implementationsauthor=Will Deacon alias=platform:arm-smmulicense=GPL v2vermagic=6.1.78-android14-11-g1a72e2f692ac-ab12000080 SMP preempt mod_unload modversions aarch64name=arm_smmuintree=Yscmversion=g1a72e2f692acdepends=qcom-scmalias=of:N*T*Carm,smmu-v1alias=of:N*T*Carm,smmu-v1C*alias=of:N*T*Carm,smmu-v2alias=of:N*T*Carm,smmu-v2C*alias=of:N*T*Carm,mmu-400alias=of:N*T*Carm,mmu-400C*alias=of:N*T*Carm,mmu-401alias=of:N*T*Carm,mmu-401C*alias=of:N*T*Carm,mmu-500alias=of:N*T*Carm,mmu-500C*alias=of:N*T*Ccavium,smmu-v2alias=of:N*T*Ccavium,smmu-v2C*alias=of:N*T*Cnvidia,smmu-500alias=of:N*T*Cnvidia,smmu-500C*alias=of:N*T*Cqcom,smmu-v2alias=of:N*T*Cqcom,smmu-v2C*       &smmu->stream_map_mutexnvidia_smmu_context_fault_bankarm-smmufailed to allocate %d irqs disabling translation s %scoherent table walk failed to set DMA mask for table walker Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d stream-matching supported, but no SMRs present! qcom,adreno-smmu address translation ops arm-smmu-context-faultiova to phys timed out on %pad. Falling back to software table walk. mmu-mastersprobing hardware configuration... found %d interrupts but expected at least %d failed to request context IRQ %d (%u) qcom,sdm845-smmu-500smmu.%paFailed to register iommu in sysfs Stage-1: %lu-bit VA -> %lu-bit IPA nvidia,tegra194-smmuFailed to turn off SAFE logic SMR mask 0x%x out of range for SMMU (0x%x) enabling workaround for Cavium erratum 27704 Unexpected global fault, this could be serious stream ID 0x%x out of range for SMMU (0x%x) #global-interruptsSMMU preserved %d boot mapping%s stream matching with %u register groupsnon- GFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x Stage-2: %lu-bit IPA -> %lu-bit PA TLB sync timed out -- SMMU may be deadlocked arm_smmu_context_faulttranslation fault! nvidia,tegra186-smmuarm-smmu global fault no translation support! SMMU address space size (0x%x) differs from mapped region size (0x%x)! impossible number of S2 context banks! cannot attach to SMMU %s whilst already attached to domain on SMMU %s failed to allocate arm_smmu_device failed to request global IRQ %d (%u) __arm_smmu_tlb_syncmarvell,ap806-smmu-5005arm-smmu: deprecated "mmu-masters" DT property in use; %s support unavailable SMMUv%d with: &smmu_domain->init_mutexmissing #global-interrupts property not probing due to mismatched DT properties nvidia,tegra234-smmustream-match-maskqcom,msm8996-smmu-v2failed to get clocks %d stage 1 translation nvidia_smmu_tlb_syncnvidia_smmu_global_fault_inst %u context banks (%u stage-2 only) Failed to register iommu arm_smmu_global_faultBlocked unknown Stream ID 0x%hx; boot with "arm-smmu.disable_bypass=0" to allow, but this may have security implications Supported page sizes: 0x%08lx cannot attach to SMMU, is it on the same bus? PAR = 0x%llx nested translation (IDR0.CTTW overridden by FW configuration) calxeda,smmu-secure-config-accessfound only %d context irq(s) but %d required stage 2 translation memory controller probe failed for %s: %d LinuxLinuxarm_smmu:CL__platform_driver_registercUplatform_driver_unregister+@log_write_mmio$Kof_device_get_match_datatRof_find_property~_printk41dev_err_probeh)of_dma_is_coherent7devm_platform_get_and_ioremap_resource1[platform_irq_countiNnplatform_get_irq devm_clk_bulk_get_allpdevm_request_threaded_irq?iommu_device_sysfs_addQQiommu_device_registerj"__pm_runtime_set_status,jpm_runtime_enable ~_dev_err(DNiommu_device_sysfs_removeғ__stack_chk_failiommu_device_unregisterJu_find_first_bit __pm_runtime_resumeK}Gclk_bulk_disableؑ|__pm_runtime_suspend|pm_runtime_force_suspend)cclk_bulk_unpreparedHalt_cb_patch_nops6t_dev_noticeclk_bulk_preparepclk_bulk_enableq__mutex_initU_dev_warn$___ratelimitAsdev_fwnode 4_raw_spin_lock_irqsavep\_raw_spin_unlock_irqrestore dma_set_maskwdma_set_coherent_mask!rklog_read_mmio^ log_post_read_mmio߼device_get_dma_attrkmalloc_cachesCukmalloc_trace/gdevice_match_fwnodeXN=driver_find_devicei!put_deviceE:#__kmallociPiommu_fwspec_free{mutex_lockUmutex_unlock zkfreec3device_link_add mMiommu_group_ref_getZUpci_bus_type\#generic_device_group"hpci_device_groupgiommu_alloc_resv_regionh__list_add_valid iommu_dma_get_resv_regionsbiommu_fwspec_add_idsیKpm_runtime_set_autosuspend_delay'UlD__pm_runtime_use_autosuspendBR_find_next_zero_bitU'alloc_io_pgtable_opse?ktime_get__const_udelaytndevm_free_irq3free_io_pgtable_opsXreport_iommu_faultk}__udelay뱣param_ops_int param_ops_bool of_device_is_compatible5?devm_krealloc6kdevm_tegra_memory_controller_get,n,?pnAnBn C nHCT nD nHF nF npG4 nG nH nI nJ nJL nKx nxK nL nDL nLP nN nO n0P nP n(Q0 nLQ\ nQ n(R n|R nRnRHnS|nHTnTnTnpUDnUn HC  L%  PXb L P 6  2  < 8h 8  < 9 #  x%H t% x%\$ x';  'X0 ' ' (Hb ( ( l)| h)- l)  ) ) )  *pV * * +* + +H0 -i<  l/eH /;T 1 ,?: 3P 3] 3`v 4% 50 5 5Jl 5~ <6  86r <6xB 6 87P  47p 87 @8 8D 8 8 J  J|l :  <` << < <` <; <  <dd < < =f = (?6 ,?(Q A A5 Am B^ B B Dl C( Cz C( HF DF` HF Fp F0 F GL pG( lG/ pG HX H H5 It It I LT L KX{ K KH  xK tKL xK L, L L[  DLDh @L DL  < (nj5 P(("4QK   (0I8@HP?c,?|k%0X7x [ L L' O| 0P N N xx xh x- x*S R Pl P Po P!  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.note.gnu.property.note.Linux.rela.exit.text.rela.init.text.hyp.text.rela.text.comment.init.plt.hyp.bss.rela.altinstructions__versions.modinfo.rela__param.note.GNU-stack.llvm_addrsig.text.ftrace_trampoline.init.eh_frame.rela.eh_frame.rela.gnu.linkonce.this_module.note.gnu.build-id.shstrtab.strtab.symtab.hyp.rodata.rela.rodata.rela.exit.data.rela.init.data.hyp.data.rela.data.BTF.rodata.str1.1of_find_propertyarm_smmu_device_cfg_probe.__keyarm_smmu_domain_alloc.__keyof_property_read_variable_u32_array__const_udelay__udelaypm_runtime_set_autosuspend_delayarm_smmu_attach_devqcom_adreno_smmu_init_contextqcom_smmu_init_contextnvidia_smmu_init_contextcavium_init_contextcavium_cfg_probe.context_countplatform_irq_countparam_ops_intof_dma_is_coherentdma_set_mask_and_coherentreport_iommu_faultarm_smmu_context_faultnvidia_smmu_context_faultarm_smmu_global_faultnvidia_smmu_global_fault__mutex_initarm_smmu_impl_initqcom_smmu_impl_initnvidia_smmu_impl_init___ratelimit_find_first_bit_find_next_zero_bitnvidia_smmu_resetarm_smmu_device_resetqcom_smmu500_resetarm_mmu500_resetdevm_tegra_memory_controller_getiommu_group_ref_getktime_getarm_smmu_iova_to_phys__pm_runtime_set_status__param_str_disable_bypass__param_disable_bypassnvidia_smmu_global_fault_inst._rsarm_smmu_context_fault._rsnvidia_smmu_context_fault_bank._rs__arm_smmu_tlb_sync._rsnvidia_smmu_tlb_sync._rsarm_smmu_global_fault.rsalt_cb_patch_nopsarm_smmu_opsarm_smmu_pm_opsfree_io_pgtable_opsalloc_io_pgtable_opsarm_smmu_s1_tlb_ops____versionsarm_smmu_get_resv_regionsiommu_dma_get_resv_regionsarm_smmu_write_nsarm_smmu_read_nsarm_smmu_test_smr_masksarm_smmu_set_pgtable_quirkskmalloc_cachesarm_smmu_unmap_pagesarm_smmu_map_pagesiommu_fwspec_add_idsdevice_get_dma_attr_dev_errarm_smmu_rmr_install_bypass_smrqcom_adreno_smmu_write_sctlrarm_smmu_driverplatform_driver_unregisteriommu_device_unregister__platform_driver_registeriommu_device_registerarm_smmu_write_s2crqcom_smmu_write_s2crplatform_get_irqdevm_free_irqdevm_request_threaded_irqmrvl_mmu500_writeqmrvl_mmu500_readqarm_smmu_device_grouppci_device_groupgeneric_device_grouplog_post_write_mmiolog_write_mmiolog_post_read_mmiolog_read_mmioqcom_adreno_smmu_get_fault_infoarm_smmu_device_shutdown_dev_warnqcom_adreno_smmu_resume_translationiommu_alloc_resv_regionqcom_adreno_smmu_implqcom_smmu_implnvidia_smmu_implcavium_implnvidia_smmu_single_implcalxeda_implarm_mmu500_implmrvl_mmu500_implparam_ops_boolqcom_adreno_smmu_set_stalldevm_clk_bulk_get_allarm_smmu_flush_iotlb_all__stack_chk_failarm_smmu_readl.compoundliteral_printkdma_set_coherent_maskdma_set_maskarm_smmu_write_context_bankqcom_adreno_smmu_alloc_context_bankmutex_unlockmutex_lockarm_smmu_of_matchqcom_smmu_client_of_matchqcom_smmu_impl_of_matcharm_smmu_enable_nestingusing_legacy_bindingusing_generic_bindingqcom_adreno_smmu_get_ttbr1_cfgqcom_adreno_smmu_set_ttbr0_cfgnvidia_smmu_write_regnvidia_smmu_read_regarm_smmu_probe_finalizenvidia_smmu_probe_finalizeiommu_device_sysfs_removearm_smmu_device_remove_raw_spin_lock_irqsavearm_smmu_of_xlate_raw_spin_unlock_irqrestoreclk_bulk_unprepareclk_bulk_preparepci_bus_typearm_smmu_def_domain_typeqcom_smmu_def_domain_typearm_smmu_pm_resumearm_smmu_runtime_resume__pm_runtime_resumeinit_module__this_modulecleanup_moduleqcom_scm_qsmmu500_wait_safe_toggleof_device_is_compatible__mod_of__arm_smmu_of_match_device_tableclk_bulk_disablearm_smmu_capableclk_bulk_enableclk_bulk_prepare_enablepm_runtime_enableqcom_scm_is_available__param_str_force_stage__param_force_stagekfreearm_smmu_domain_freeiommu_fwspec_freedev_fwnode__kcfi_typeid_device_match_fwnodeof_match_nodeplatform_get_resourcedevm_ioremap_resourcedevm_platform_get_and_ioremap_resourceput_deviceof_match_devicearm_smmu_release_devicearm_smmu_probe_devicetegra_mc_probe_devicedriver_find_device_dev_noticekmalloc_tracedev_err_probeqcom_smmu_cfg_probecavium_cfg_probearm_smmu_device_cfg_probemrvl_mmu500_cfg_probearm_smmu_device_probe__pm_runtime_use_autosuspendarm_smmu_pm_suspendarm_smmu_runtime_suspend__pm_runtime_suspendpm_runtime_force_suspend__list_add_validwriteq_relaxedreadq_relaxedwritel_relaxedreadl_relaxediommu_device_sysfs_adddevice_link_adddevm_kmalloc__kmallocdevm_kreallocarm_smmu_domain_allocarm_smmu_iotlb_sync__arm_smmu_tlb_syncqcom_smmu_tlb_syncnvidia_smmu_tlb_syncof_device_get_match_data_note_9$d.99$d.89$d.79$d.69$d.59__UNIQUE_ID_alias349$d.49__UNIQUE_ID_alias339$d.39$d.29$d.19$d.109$d.9$x.98$x.88$x.78__UNIQUE_ID_disable_bypass468$x.68$x.58__UNIQUE_ID_alias348$x.48__UNIQUE_ID_alias338$x.38$x.28$d.28$d.118$x.18$x.108$x.8$d.8$d.97$d.87$d.77__UNIQUE_ID_disable_bypasstype467$d.67$d.57__UNIQUE_ID_alias347$d.47__UNIQUE_ID_alias337$d.37$d.27$d.117$d.17$d.107$d.7$x.96$x.86$x.76__UNIQUE_ID_force_stage466$x.66$x.56__UNIQUE_ID_license646__UNIQUE_ID_alias346$x.46$d.46__UNIQUE_ID_depends336$x.36$d.36$x.26$d.116$x.16$x.106$x.6$d.95$d.85$d.75__UNIQUE_ID_force_stagetype465$d.65$d.55__UNIQUE_ID_alias645__UNIQUE_ID_alias345$d.45__UNIQUE_ID_scmversion335$d.35$d.125$d.25$d.115$d.15$d.105nvidia_smmu_g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Farm_smmu_match_dataarm_smmu_arch_versionARM_SMMU_V1ARM_SMMU_V1_64KARM_SMMU_V2arm_smmu_implementationGENERIC_SMMUARM_MMU500CAVIUM_SMMUV2QCOM_SMMUV2arm_smmu_cbar_typeCBAR_TYPE_S2_TRANSCBAR_TYPE_S1_TRANS_S2_BYPASSCBAR_TYPE_S1_TRANS_S2_FAULTCBAR_TYPE_S1_TRANS_S2_TRANSarm_smmu_context_fmtARM_SMMU_CTX_FMT_NONEARM_SMMU_CTX_FMT_AARCH64ARM_SMMU_CTX_FMT_AARCH32_LARM_SMMU_CTX_FMT_AARCH32_Sarm_smmu_domain_stageARM_SMMU_DOMAIN_S1ARM_SMMU_DOMAIN_S2ARM_SMMU_DOMAIN_NESTEDARM_SMMU_DOMAIN_BYPASSarm_smmu_s2cr_typeS2CR_TYPE_TRANSS2CR_TYPE_BYPASSS2CR_TYPE_FAULTarm_smmu_s2cr_privcfgS2CR_PRIVCFG_DEFAULTS2CR_PRIVCFG_DIPANS2CR_PRIVCFG_UNPRIVS2CR_PRIVCFG_PRIVarm_smmu_domainpgtbl_opspgtbl_quirksflush_opsinit_mutexarm_smmu_devicenumpagepgshiftimplnum_context_banksnum_s2_context_bankscontext_mapirptndxnum_mapping_groupsstreamid_masksmr_mask_masksmrss2crsstream_map_mutexva_sizeipa_sizepa_sizenum_context_irqsglobal_sync_lockarm_smmu_implread_reg64write_reg64cfg_probeinit_contexttlb_syncglobal_faultcontext_faultalloc_context_bankwrite_s2crwrite_sctlrarm_smmu_cbarm_smmu_cfgcbndxcbarflush_walk_prefer_tlbiasidarm_smmu_smrarm_smmu_s2crprivcfgiommu_iort_rmr_datanum_sidsarm_smmu_master_cfgsmendxarm_smmu_device_cfg_probearm_smmu_global_faultarm_smmu_domain_alloc__arm_smmu_tlb_syncarm_smmu_context_faultarm_smmu_write_context_bankarm_smmu_device_probeclk_bulk_prepare_enablearm_smmu_rmr_install_bypass_smrarm_smmu_device_resetarm_smmu_test_smr_masksarm_smmu_device_removearm_smmu_device_shutdownarm_smmu_readlarm_smmu_write_s2crarm_smmu_capablearm_smmu_probe_devicearm_smmu_release_devicearm_smmu_probe_finalizearm_smmu_device_grouparm_smmu_get_resv_regionsarm_smmu_of_xlatearm_smmu_def_domain_typearm_smmu_attach_devarm_smmu_map_pagesarm_smmu_unmap_pagesarm_smmu_flush_iotlb_allarm_smmu_iotlb_syncarm_smmu_iova_to_physarm_smmu_enable_nestingarm_smmu_set_pgtable_quirksarm_smmu_domain_freearm_smmu_tlb_inv_context_s1arm_smmu_tlb_inv_walk_s1arm_smmu_tlb_inv_range_s1arm_smmu_tlb_add_page_s1arm_smmu_tlb_inv_context_s2arm_smmu_tlb_inv_walk_s2arm_smmu_tlb_inv_range_s2arm_smmu_tlb_add_page_s2arm_smmu_tlb_inv_walk_s2_v1arm_smmu_tlb_add_page_s2_v1arm_smmu_runtime_suspendarm_smmu_pm_suspendarm_smmu_runtime_resumearm_smmu_pm_resumecavium_smmuid_basecavium_cfg_probearm_mmu500_resetarm_smmu_impl_initsmmu_domainpgtbl_cfgcavium_init_contextarm_smmu_read_nsarm_smmu_write_nsmrvl_mmu500_readqmrvl_mmu500_writeqmrvl_mmu500_cfg_probenvidia_smmunvidia_smmu_tlb_syncnvidia_smmu_impl_initnvidia_smmu_init_contextnvidia_smmu_probe_finalizenvidia_smmu_read_regnvidia_smmu_write_regnvidia_smmu_read_reg64nvidia_smmu_write_reg64nvidia_smmu_resetnvidia_smmu_global_faultnvidia_smmu_context_faultqcom_smmubypass_quirkbypass_cbndxstall_enabledqcom_smmu_configadreno_smmu_privget_ttbr1_cfgset_ttbr0_cfgget_fault_infoset_stallresume_translationadreno_smmu_fault_infocontextidrfsynr0fsynr1cbfrsynraqcom_smmu_impl_initqcom_smmu500_resetqcom_adreno_smmu_init_contextqcom_smmu_tlb_syncqcom_smmu_def_domain_typeqcom_adreno_smmu_alloc_context_bankqcom_adreno_smmu_write_sctlrqcom_adreno_smmu_get_ttbr1_cfgqcom_adreno_smmu_set_ttbr0_cfgqcom_adreno_smmu_get_fault_infoqcom_adreno_smmu_set_stallqcom_adreno_smmu_resume_translationqcom_smmu_cfg_probeqcom_smmu_init_contextqcom_smmu_write_s2crv@,cp^qr@hHO$lJ@H7( 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