7 #define UART0_BASE      0xef600300
8 #define UART1_BASE      0xef600400
9 #define UCR0_MASK       0x0000007f
10 #define UCR1_MASK       0x00007f00
11 #define UCR0_UDIV_POS   0
15 #define UART_RBR		0x00
16 #define UART_THR		0x00
17 #define UART_IER		0x01
18 #define UART_IIR		0x02
19 #define UART_FCR		0x02
20 #define UART_LCR		0x03
21 #define UART_MCR		0x04
22 #define UART_LSR		0x05
23 #define UART_MSR		0x06
24 #define UART_SCR		0x07
25 #define UART_DLL		0x00
26 #define UART_DLM		0x01
31 #define asyncLSRDataReady1            0x01
32 #define asyncLSROverrunError1         0x02
33 #define asyncLSRParityError1          0x04
34 #define asyncLSRFramingError1         0x08
35 #define asyncLSRBreakInterrupt1       0x10
36 #define asyncLSRTxHoldEmpty1          0x20
37 #define asyncLSRTxShiftEmpty1         0x40
38 #define asyncLSRRxFifoError1          0x80
71 		out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01);  in rt_serial_open()
128 					device->read_index = 0;  in rt_serial_read()
150 		RT_ASSERT(0);  in rt_serial_read()
154 	RT_ASSERT(0);  in rt_serial_read()
170 		RT_ASSERT(0);  in rt_serial_write()
175 		RT_ASSERT(0);  in rt_serial_write()
188 				while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);  in rt_serial_write()
192 			while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);  in rt_serial_write()
203 			while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);  in rt_serial_write()
231 	if (status & 0x01)  in rt_serial_isr()
235 		while (status & 0x01)  in rt_serial_isr()
241 			device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base));  in rt_serial_isr()
244 				device->save_index = 0;  in rt_serial_isr()
251 					device->read_index = 0;  in rt_serial_isr()
261 					asyncLSRBreakInterrupt1 )) != 0)  in rt_serial_isr()
294 	rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer));  in rt_hw_serial_init()
295 	device->read_index = device->save_index = 0;  in rt_hw_serial_init()
297 	out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80);	/* set DLAB bit */  in rt_hw_serial_init()
300 	out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */  in rt_hw_serial_init()
301 	out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00);	/* disable FIFO */  in rt_hw_serial_init()
302 	out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00);	/* no modem control DTR RTS */  in rt_hw_serial_init()
305 	out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00);	/* set scratchpad */  in rt_hw_serial_init()
306 	out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00);	/* set interrupt enable reg */  in rt_hw_serial_init()