Lines Matching full:tx
556 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
557 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
558 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
559 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
566 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
567 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
568 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
569 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
570 #define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
571 #define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
572 #define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
573 #define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
574 #define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
575 #define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
576 #define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
577 #define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
578 #define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
579 #define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
580 #define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
581 #define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
582 #define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
583 #define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
584 #define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
585 #define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
586 #define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
587 #define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
588 #define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
589 #define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
590 #define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
591 #define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
592 #define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
593 #define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
594 #define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
595 #define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
596 #define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
597 #define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
670 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
671 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
672 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
673 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
678 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
679 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
680 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */