Lines Matching full:rx
561 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
562 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
563 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
564 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
598 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
599 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
600 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
601 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
602 #define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
603 #define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
604 #define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
605 #define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
606 #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
607 #define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
608 #define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
609 #define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
610 #define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
611 #define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
612 #define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
613 #define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
614 #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
615 #define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
616 #define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
617 #define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
618 #define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
619 #define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
620 #define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
621 #define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
622 #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
623 #define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
624 #define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
625 #define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
626 #define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
627 #define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
628 #define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
629 #define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
630 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
631 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
632 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
633 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
634 #define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
635 #define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
636 #define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
637 #define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
638 #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
639 #define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
640 #define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
641 #define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
642 #define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
643 #define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
644 #define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
645 #define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
646 #define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
647 #define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
648 #define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
649 #define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
650 #define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
651 #define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
652 #define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
653 #define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
654 #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
655 #define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
656 #define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
657 #define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
658 #define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
659 #define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
660 #define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
661 #define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
674 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
675 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
676 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
677 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
681 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
682 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
683 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
684 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */