Lines Matching +full:ram +full:- +full:up
21 * MA 02111-1307 USA
27 * XXX - DANGER
29 * UNTIL THEY ARE RELOCATED TO RAM. Additionally, I do not
46 * Build up a 'mfdcr' instruction formatted as follows:
49 * ---------------|--------------|--------------|----|
55 * OPCD = opcode - 31
56 * RT = destination register - %r3 return register
58 * XO = extended opcode - 323
59 * CR = CR[CR0] NOT undefined - 0
77 .Lfe1: .size _create_MFDCR,.Lfe1-_create_MFDCR
91 * Build up a 'mtdcr' instruction formatted as follows:
94 * ---------------|--------------|--------------|----|
100 * OPCD = opcode - 31
101 * RS = source register - %r4
103 * XO = extended opcode - 451
104 * CR = CR[CR0] NOT undefined - 0
122 .Lfe2: .size _create_MTDCR,.Lfe2-_create_MTDCR
132 /* XXX - This is self modifying code, hence */
141 stwu r1, -32(r1) /* Save back chain and move SP */
145 /* XXX - we build this instuction up on the fly. */
152 .Lfe3: .size get_dcr,.Lfe3-get_dcr
162 * XXX - This is self modifying code, hence
171 stwu r1, -32(r1) /* Save back chain and move SP */
175 /* XXX - we build this instuction up on the fly. */
182 .Lfe4: .size set_dcr,.Lfe4-set_dcr