46 void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)  in r4k_icache_flush_range()  argument
50     if (size > g_mips_core.icache_size)  in r4k_icache_flush_range()
59         end = ((addr + size) - 1) & ~(ic_lsize - 1);  in r4k_icache_flush_range()
70 void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)  in r4k_icache_lock_range()  argument
76     end = ((addr + size) - 1) & ~(ic_lsize - 1);  in r4k_icache_lock_range()
86 void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)  in r4k_dcache_inv()  argument
92     end = ((addr + size) - 1) & ~(dc_lsize - 1);  in r4k_dcache_inv()
102 void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)  in r4k_dcache_wback_inv()  argument
106     if (size >= g_mips_core.dcache_size)  in r4k_dcache_wback_inv()
115         end = ((addr + size) - 1) & ~(dc_lsize - 1);  in r4k_dcache_wback_inv()
126 #define dma_cache_wback_inv(start,size) \  argument
127     do { (void) (start); (void) (size); } while (0)
128 #define dma_cache_wback(start,size) \  argument
129     do { (void) (start); (void) (size); } while (0)
130 #define dma_cache_inv(start,size)   \  argument
131     do { (void) (start); (void) (size); } while (0)
134 void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction)  in r4k_dma_cache_sync()  argument
139             r4k_dcache_wback_inv(addr, size);  in r4k_dma_cache_sync()
143             r4k_dcache_wback_inv(addr, size);  in r4k_dma_cache_sync()
147             dma_cache_wback_inv(addr, size);  in r4k_dma_cache_sync()