Lines Matching +full:2 +full:m
17 /* MPLL=2*12*100/6=400MHz */
18 #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
19 #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
22 #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
23 #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
26 #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
28 #define PDIVN 0x1 /* PCLK = HCLK / 2 */
39 rt_uint8_t m, p, s; in rt_hw_get_clock() local
42 m = (val>>12)&0xff; in rt_hw_get_clock()
46 FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100; in rt_hw_get_clock()
49 m = (val>>1)&3; in rt_hw_get_clock()
52 switch (m) { in rt_hw_get_clock()
59 case 2: in rt_hw_get_clock()
60 if(s&2) in rt_hw_get_clock()
63 HCLK = FCLK>>2; in rt_hw_get_clock()