Lines Matching +full:1 +full:m
18 #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
22 #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
24 #define UPL_SDIV 1 /* s=UPL_SDIV=1 */
25 /* System clock divider FCLK:HCLK:PCLK=1:4:8 */
39 rt_uint8_t m, p, s; in rt_hw_get_clock() local
42 m = (val>>12)&0xff; in rt_hw_get_clock()
46 FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100; in rt_hw_get_clock()
49 m = (val>>1)&3; in rt_hw_get_clock()
50 p = val&1; in rt_hw_get_clock()
52 switch (m) { in rt_hw_get_clock()
56 case 1: in rt_hw_get_clock()
57 HCLK = FCLK>>1; in rt_hw_get_clock()
66 if(s&1) in rt_hw_get_clock()
74 PCLK = HCLK>>1; in rt_hw_get_clock()
91 CLKDIVN = (hdivn<<1) | pdivn; in rt_hw_set_divider()