Lines Matching full:6
170 ;// <o4.6> USB Host Enable
190 ;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6
204 ;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6
233 BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset
237 MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset
246 ;// <o1.27> ST6: Use UB/LB for Bank 6
247 ;// <o1.26> WS6: Enable Wait Status for Bank 6
248 ;// <o1.24..25> DW6: Data Bus Width for Bank 6
267 ;// <o1.6> WS1: Enable Wait Status for Bank 1
280 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
281 ;// <o2.6..7> Tcoh: Chip Selection Hold Time after nOE
286 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
297 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
298 ;// <o3.6..7> Tcoh: Chip Selection Hold Time after nOE
303 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
314 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
315 ;// <o4.6..7> Tcoh: Chip Selection Hold Time after nOE
320 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
331 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
332 ;// <o5.6..7> Tcoh: Chip Selection Hold Time after nOE
337 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
348 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
349 ;// <o6.6..7> Tcoh: Chip Selection Hold Time after nOE
354 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
365 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
366 ;// <o7.6..7> Tcoh: Chip Selection Hold Time after nOE
371 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
375 ;// <h> Bank 6 Control Register (BANKCON6)
384 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
385 ;// <o8.6..7> Tcoh: Chip Selection Hold Time after nOE
392 ;// <i> For SDRAM 6 cycles setting is not allowed
393 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
407 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
408 ;// <o9.6..7> Tcoh: Chip Selection Hold Time after nOE
415 ;// <i> For SDRAM 6 cycles setting is not allowed
416 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
429 ;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks
440 ;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB
444 ;// <h> SDRAM Mode Register Set Register 6 (MRSRB6)
449 ;// <o12.4..6> CL: CAS Latency
461 ;// <o13.4..6> CL: CAS Latency
521 ;// <o1.6> GPA6 <0=> Output <1=> ADDR21
542 ;// <o1.6..7> GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved
552 ;// <o2.6> GPB6 Pull-up Disable
568 ;// <o1.28..29> GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved
579 ;// <o1.6..7> GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
594 ;// <o2.6> GPC6 Pull-up Disable
621 ;// <o1.6..7> GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved
636 ;// <o2.6> GPD6 Pull-up Disable
665 ;// <o1.6..7> GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN
678 ;// <o2.6> GPE6 Pull-up Disable
694 ;// <o1.12..13> GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved
697 ;// <o1.6..7> GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved
704 ;// <o2.6> GPF6 Pull-up Disable
731 ;// <o1.6..7> GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1
746 ;// <o2.6> GPG6 Pull-up Disable
768 ;// <o1.6..7> GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved
778 ;// <o2.6> GPH6 Pull-up Disable
799 ;// <o1.12..13> GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved
802 ;// <o1.6..7> GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved
814 ;// <o2.6> GPJ6 Pull-up Disable