Lines Matching full:1
108 ;// <0=> 16 <1=> 32 <2=> 64 <3=> 128
116 WT_SETUP EQU 1
143 ;// <o2.0..1> s: Post Divider s Value <0-3>
152 ;// <o3.0..1> s: Post Divider s Value <0-3>
185 ;// <1=> UCLK = UPLL clock / 2
186 ;// <o6.1..2> HDIVN: HCLK Select
188 ;// <1=> HCLK = FCLK / 2
193 ;// <1=> PCLK = HCLK / 2
198 ;// <1=> ARM core runs at HCLK
201 ;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8
204 ;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6
207 ;// <1=> CAMCLK = UPLL / CAMCLK_DIV
209 ;// <i> Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1))
210 ;// <i> Divider is used only if CAMCLK_SEL = 1
228 BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset
245 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
249 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
253 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
257 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
261 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
265 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
266 ;// <o1.7> ST1: Use UB/LB for Bank 1
267 ;// <o1.6> WS1: Enable Wait Status for Bank 1
268 ;// <o1.4..5> DW1: Data Bus Width for Bank 1
269 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved
270 ;// <o1.1..2> DW0: Indicate Data Bus Width for Bank 0
271 ;// <1=> 16-bit <2=> 32-bit
275 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
277 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
279 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
282 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
284 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
286 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
287 ;// <o2.0..1> PMC: Page Mode Configuration
288 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
290 ;// <h> Bank 1 Control Register (BANKCON1)
292 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
294 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
296 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
299 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
301 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
303 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
304 ;// <o3.0..1> PMC: Page Mode Configuration
305 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
309 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
311 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
313 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
316 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
318 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
320 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
321 ;// <o4.0..1> PMC: Page Mode Configuration
322 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
326 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
328 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
330 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
333 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
335 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
337 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
338 ;// <o5.0..1> PMC: Page Mode Configuration
339 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
343 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
345 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
347 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
350 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
352 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
354 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
355 ;// <o6.0..1> PMC: Page Mode Configuration
356 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
360 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
362 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
364 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
367 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
369 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
371 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
372 ;// <o7.0..1> PMC: Page Mode Configuration
373 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
379 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
381 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
383 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
386 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
388 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
393 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
394 ;// <o8.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
402 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
404 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
406 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
409 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
411 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
416 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
417 ;// <o9.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
424 ;// <0=> CBR/Auto Refresh <1=> Self Refresh
426 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved
429 ;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks
431 ;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
437 ;// <0=> SCLK is always active <1=> SCLK is active only during the access
439 ;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB
442 ;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
450 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
454 ;// <0=> 1 (Fixed)
462 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
466 ;// <0=> 1 (Fixed)
501 GP_SETUP EQU 1
505 ;// <o1.22> GPA22 <0=> Output <1=> nFCE
506 ;// <o1.21> GPA21 <0=> Output <1=> nRSTOUT
507 ;// <o1.20> GPA20 <0=> Output <1=> nFRE
508 ;// <o1.19> GPA19 <0=> Output <1=> nFWE
509 ;// <o1.18> GPA18 <0=> Output <1=> ALE
510 ;// <o1.17> GPA17 <0=> Output <1=> CLE
511 ;// <o1.16> GPA16 <0=> Output <1=> nGCS[5]
512 ;// <o1.15> GPA15 <0=> Output <1=> nGCS[4]
513 ;// <o1.14> GPA14 <0=> Output <1=> nGCS[3]
514 ;// <o1.13> GPA13 <0=> Output <1=> nGCS[2]
515 ;// <o1.12> GPA12 <0=> Output <1=> nGCS[1]
516 ;// <o1.11> GPA11 <0=> Output <1=> ADDR26
517 ;// <o1.10> GPA10 <0=> Output <1=> ADDR25
518 ;// <o1.9> GPA9 <0=> Output <1=> ADDR24
519 ;// <o1.8> GPA8 <0=> Output <1=> ADDR23
520 ;// <o1.7> GPA7 <0=> Output <1=> ADDR22
521 ;// <o1.6> GPA6 <0=> Output <1=> ADDR21
522 ;// <o1.5> GPA5 <0=> Output <1=> ADDR20
523 ;// <o1.4> GPA4 <0=> Output <1=> ADDR19
524 ;// <o1.3> GPA3 <0=> Output <1=> ADDR18
525 ;// <o1.2> GPA2 <0=> Output <1=> ADDR17
526 ;// <o1.1> GPA1 <0=> Output <1=> ADDR16
527 ;// <o1.0> GPA0 <0=> Output <1=> ADDR0
535 ;// <o1.20..21> GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved
536 ;// <o1.18..19> GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved
537 ;// <o1.16..17> GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved
538 ;// <o1.14..15> GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved
539 ;// <o1.12..13> GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved
540 ;// <o1.10..11> GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved
541 ;// <o1.8..9> GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved
542 ;// <o1.6..7> GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved
543 ;// <o1.4..5> GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved
544 ;// <o1.2..3> GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved
545 ;// <o1.0..1> GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
557 ;// <o2.1> GPB1 Pull-up Disable
567 ;// <o1.30..31> GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved
568 ;// <o1.28..29> GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved
569 ;// <o1.26..27> GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved
570 ;// <o1.24..25> GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved
571 ;// <o1.22..23> GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved
572 ;// <o1.20..21> GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved
573 ;// <o1.18..19> GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved
574 ;// <o1.16..17> GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved
575 ;// <o1.14..15> GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved
576 ;// <o1.12..13> GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved
577 ;// <o1.10..11> GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved
578 ;// <o1.8..9> GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI
579 ;// <o1.6..7> GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
580 ;// <o1.4..5> GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
581 ;// <o1.2..3> GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved
582 ;// <o1.0..1> GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved
599 ;// <o2.1> GPC1 Pull-up Disable
609 ;// <o1.30..31> GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0
610 ;// <o1.28..29> GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1
611 ;// <o1.26..27> GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved
612 ;// <o1.24..25> GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved
613 ;// <o1.22..23> GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved
614 ;// <o1.20..21> GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1
615 ;// <o1.18..19> GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1
616 ;// <o1.16..17> GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1
617 ;// <o1.14..15> GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved
618 ;// <o1.12..13> GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved
619 ;// <o1.10..11> GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved
620 ;// <o1.8..9> GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved
621 ;// <o1.6..7> GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved
622 ;// <o1.4..5> GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved
623 ;// <o1.2..3> GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved
624 ;// <o1.0..1> GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved
641 ;// <o2.1> GPD1 Pull-up Disable
651 ;// <o1.30..31> GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
653 ;// <o1.28..29> GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
655 ;// <o1.26..27> GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved
656 ;// <o1.24..25> GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved
657 ;// <o1.22..23> GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved
658 ;// <o1.20..21> GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved
659 ;// <o1.18..19> GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved
660 ;// <o1.16..17> GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved
661 ;// <o1.14..15> GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved
662 ;// <o1.12..13> GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved
663 ;// <o1.10..11> GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved
664 ;// <o1.8..9> GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT
665 ;// <o1.6..7> GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN
666 ;// <o1.4..5> GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET
667 ;// <o1.2..3> GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK
668 ;// <o1.0..1> GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC
683 ;// <o2.1> GPE1 Pull-up Disable
693 ;// <o1.14..15> GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved
694 ;// <o1.12..13> GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved
695 ;// <o1.10..11> GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved
696 ;// <o1.8..9> GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved
697 ;// <o1.6..7> GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved
698 ;// <o1.4..5> GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved
699 ;// <o1.2..3> GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved
700 ;// <o1.0..1> GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved
709 ;// <o2.1> GPF1 Pull-up Disable
713 GPF_SETUP EQU 1
719 ;// <o1.30..31> GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved
720 ;// <o1.28..29> GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved
721 ;// <o1.26..27> GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved
722 ;// <o1.24..25> GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved
723 ;// <o1.22..23> GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1]
724 ;// <o1.20..21> GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1
725 ;// <o1.18..19> GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1
726 ;// <o1.16..17> GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved
727 ;// <o1.14..15> GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1
728 ;// <o1.12..13> GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1
729 ;// <o1.10..11> GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1
730 ;// <o1.8..9> GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN
731 ;// <o1.6..7> GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1
732 ;// <o1.4..5> GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0
733 ;// <o1.2..3> GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved
734 ;// <o1.0..1> GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved
751 ;// <o2.1> GPG1 Pull-up Disable
761 ;// <o1.20..21> GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved
762 ;// <o1.18..19> GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved
763 ;// <o1.16..17> GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved
764 ;// <o1.14..15> GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1
765 ;// <o1.12..13> GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1
766 ;// <o1.10..11> GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved
767 ;// <o1.8..9> GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved
768 ;// <o1.6..7> GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved
769 ;// <o1.4..5> GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved
770 ;// <o1.2..3> GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved
771 ;// <o1.0..1> GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved
783 ;// <o2.1> GPH1 Pull-up Disable
793 ;// <o1.24..25> GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved
794 ;// <o1.22..23> GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved
795 ;// <o1.20..21> GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved
796 ;// <o1.18..19> GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved
797 ;// <o1.16..17> GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved
798 ;// <o1.14..15> GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved
799 ;// <o1.12..13> GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved
800 ;// <o1.10..11> GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved
801 ;// <o1.8..9> GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved
802 ;// <o1.6..7> GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved
803 ;// <o1.4..5> GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved
804 ;// <o1.2..3> GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved
805 ;// <o1.0..1> GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved
819 ;// <o2.1> GPJ1 Pull-up Disable
1116 CMP r1, #1