40 void mmu_setttbase(register rt_uint32_t i)  in mmu_setttbase()  argument
42 	asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));  in mmu_setttbase()
45 void mmu_set_domain(register rt_uint32_t i)  in mmu_set_domain()  argument
47 	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));  in mmu_set_domain()
52 	register rt_uint32_t i;  in mmu_enable()  local
55 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_enable()
57 	i |= 0x1;  in mmu_enable()
60 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_enable()
65 	register rt_uint32_t i;  in mmu_disable()  local
68 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_disable()
70 	i &= ~0x1;  in mmu_disable()
73 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_disable()
78 	register rt_uint32_t i;  in mmu_enable_icache()  local
81 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_enable_icache()
83 	i |= (1 << 12);  in mmu_enable_icache()
86 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_enable_icache()
91 	register rt_uint32_t i;  in mmu_enable_dcache()  local
94 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_enable_dcache()
96 	i |= (1 << 2);  in mmu_enable_dcache()
99 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_enable_dcache()
104 	register rt_uint32_t i;  in mmu_disable_icache()  local
107 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_disable_icache()
109 	i &= ~(1 << 12);  in mmu_disable_icache()
112 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_disable_icache()
117 	register rt_uint32_t i;  in mmu_disable_dcache()  local
120 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_disable_dcache()
122 	i &= ~(1 << 2);  in mmu_disable_dcache()
125 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_disable_dcache()
130 	register rt_uint32_t i;  in mmu_enable_alignfault()  local
133 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_enable_alignfault()
135 	i |= (1 << 1);  in mmu_enable_alignfault()
138 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_enable_alignfault()
143 	register rt_uint32_t i;  in mmu_disable_alignfault()  local
146 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_disable_alignfault()
148 	i &= ~(1 << 1);  in mmu_disable_alignfault()
151 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_disable_alignfault()
171 void mmu_setttbase(rt_uint32_t i)  in mmu_setttbase()  argument
175         mcr p15, 0, i, c2, c0, 0  in mmu_setttbase()
179 void mmu_set_domain(rt_uint32_t i)  in mmu_set_domain()  argument
183         mcr p15,0, i, c3, c0,  0  in mmu_set_domain()
318     volatile int i,nSec;  in mmu_setmtt()  local
321     for(i=0;i<=nSec;i++)  in mmu_setmtt()
323 		*pTT = attr |(((paddrStart>>20)+i)<<20);  in mmu_setmtt()
330 	int i,j;  in rt_hw_mmu_init()  local
341 	for(i=0;i<64;i++)  in rt_hw_mmu_init()
343 			mmu_clean_invalidated_cache_index((i<<26)|(j<<5));  in rt_hw_mmu_init()