18     ARM_PMU_EVENT_PMNC_SW_INCR      = 0x00,
19     ARM_PMU_EVENT_L1_ICACHE_REFILL  = 0x01,
20     ARM_PMU_EVENT_ITLB_REFILL       = 0x02,
21     ARM_PMU_EVENT_L1_DCACHE_REFILL  = 0x03,
22     ARM_PMU_EVENT_L1_DCACHE_ACCESS  = 0x04,
23     ARM_PMU_EVENT_DTLB_REFILL       = 0x05,
24     ARM_PMU_EVENT_MEM_READ          = 0x06,
25     ARM_PMU_EVENT_MEM_WRITE         = 0x07,
26     ARM_PMU_EVENT_INSTR_EXECUTED    = 0x08,
27     ARM_PMU_EVENT_EXC_TAKEN         = 0x09,
28     ARM_PMU_EVENT_EXC_EXECUTED      = 0x0A,
29     ARM_PMU_EVENT_CID_WRITE         = 0x0B,
33 #define ARM_PMU_PMCR_E   (0x01 << 0)
35 #define ARM_PMU_PMCR_P   (0x01 << 1)
37 #define ARM_PMU_PMCR_C   (0x01 << 2)
39 #define ARM_PMU_PMCR_D   (0x01 << 3)
47     asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));  in rt_hw_pmu_enable_cnt()
53     asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));  in rt_hw_pmu_enable_cnt()
56     pmcntenset = ~0;  in rt_hw_pmu_enable_cnt()
57     asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset));  in rt_hw_pmu_enable_cnt()
59     asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset));  in rt_hw_pmu_enable_cnt()
65     asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));  in rt_hw_pmu_get_control()
73     asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg));  in rt_hw_pmu_get_ceid()
80     asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt));  in rt_hw_pmu_get_cnten()
88     asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));  in rt_hw_pmu_reset_cycle()
90     asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));  in rt_hw_pmu_reset_cycle()
98     asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));  in rt_hw_pmu_reset_event()
100     asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));  in rt_hw_pmu_reset_event()
108     asm volatile ("mrc  p15, 0, %0, c9, c13, 0" : "=r"(cyc));  in rt_hw_pmu_get_cycle()
116     asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx));  in rt_hw_pmu_select_counter()
127     asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve));  in rt_hw_pmu_select_event()
136     asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg));  in rt_hw_pmu_read_counter()
144     asm ("mrc  p15, 0, %0, c9, c12, 3" : "=r"(reg));  in rt_hw_pmu_get_ovsr()
150     asm ("mcr  p15, 0, %0, c9, c12, 3" : : "r"(reg));  in rt_hw_pmu_clear_ovsr()