Lines Matching full:active

511 ;//       <h> Dynamic Memory Active to Precharge Command Period Register (EMCDynamictRAS)
512 ;//         <o1.0..3> tRAS: Active to precharge command period <1-16> <#-1>
522 ;//       <h> Dynamic Memory Last Data Out to Active Time Register (EMCDynamictAPR)
523 ;//         <o3.0..3> tAPR: Last-data-out to active command time <1-16> <#-1>
527 ;//       <h> Dynamic Memory Data-in to Active Command Time Register (EMCDynamictDAL)
528 ;//         <o4.0..3> tDAL: Data-in to active command time <1-16> <#-1>
537 ;//       <h> Dynamic Memory Active to Active Command Period Register (EMCDynamictRC)
538 ;//         <o6.0..4> tRC: Active to active command period <1-32> <#-1>
543 ;//         <o7.0..4> tRFC: Auto-refresh period and auto-refresh to active command period <1-32> <#…
548 ;//         <o8.0..4> tXSR: Exit self-refresh to active command time <1-32> <#-1>
552 ;//       <h> Dynamic Memory Active Bank A to Active Bank B Time Register (EMCDynamicRRD)
553 ;//         <o9.0..3> tRRD: Active bank A to active bank B latency <1-16> <#-1>
557 ;//       <h> Dynamic Memory Load Mode Register to Active Command Time (EMCDynamictMRD)
558 ;//         <o10.0..3> tMRD: Load mode register to active command time <1-16> <#-1>
612 ;//         <o0.0..1> RAS: RAS latency (active to read/write delay)
659 ;//         <o0.0..1> RAS: RAS latency (active to read/write delay)
705 ;//         <o0.0..1> RAS: RAS latency (active to read/write delay)
751 ;//         <o0.0..1> RAS: RAS latency (active to read/write delay)
779 ;//           <0=> Active LOW chip select
780 ;//           <1=> Active HIGH chip select
846 ;//           <0=> Active LOW chip select
847 ;//           <1=> Active HIGH chip select
913 ;//           <0=> Active LOW chip select
914 ;//           <1=> Active HIGH chip select
980 ;//           <0=> Active LOW chip select
981 ;//           <1=> Active HIGH chip select