13 void mmu_setttbase(rt_uint32_t i)  in mmu_setttbase()  argument
32 			mcr p15, 0, i, c2, c0, 0  in mmu_setttbase()
36 void mmu_set_domain(rt_uint32_t i)  in mmu_set_domain()  argument
40 		mcr p15,0, i, c3, c0,  0  in mmu_set_domain()
232 void mmu_setttbase(register rt_uint32_t i)  in mmu_setttbase()  argument
246 	asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));  in mmu_setttbase()
249 void mmu_set_domain(register rt_uint32_t i)  in mmu_set_domain()  argument
251 	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));  in mmu_set_domain()
256 	register rt_uint32_t i;  in mmu_enable()  local
259 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_enable()
261 	i |= 0x1;  in mmu_enable()
264 	i |= (1 << 23); /* support for ARMv6 MMU features */  in mmu_enable()
265 	i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */  in mmu_enable()
268 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_enable()
273 	register rt_uint32_t i;  in mmu_disable()  local
276 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_disable()
278 	i &= ~0x1;  in mmu_disable()
281 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_disable()
286 	register rt_uint32_t i;  in mmu_enable_icache()  local
289 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_enable_icache()
291 	i |= (1 << 12);  in mmu_enable_icache()
294 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_enable_icache()
299 	register rt_uint32_t i;  in mmu_enable_dcache()  local
302 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_enable_dcache()
304 	i |= (1 << 2);  in mmu_enable_dcache()
307 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_enable_dcache()
312 	register rt_uint32_t i;  in mmu_disable_icache()  local
315 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_disable_icache()
317 	i &= ~(1 << 12);  in mmu_disable_icache()
320 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_disable_icache()
325 	register rt_uint32_t i;  in mmu_disable_dcache()  local
328 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_disable_dcache()
330 	i &= ~(1 << 2);  in mmu_disable_dcache()
333 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_disable_dcache()
338 	register rt_uint32_t i;  in mmu_enable_alignfault()  local
341 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_enable_alignfault()
343 	i |= (1 << 1);  in mmu_enable_alignfault()
346 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_enable_alignfault()
351 	register rt_uint32_t i;  in mmu_disable_alignfault()  local
354 	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));  in mmu_disable_alignfault()
356 	i &= ~(1 << 1);  in mmu_disable_alignfault()
359 	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));  in mmu_disable_alignfault()
435 	volatile int i, nSec;  in mmu_create_pgd()  local
438 	for(i = 0; i <= nSec; i++)  in mmu_create_pgd()
440 		*pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20);  in mmu_create_pgd()
449 	int i;  in mmu_create_pte()  local
460 	for(i = 0; i < total_page; i++)  in mmu_create_pte()
477 		*p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12);  in mmu_create_pte()
508 	/* disable I/D cache */  in rt_hw_mmu_init()