Lines Matching full:mode

14 ; Mode, correspords to bits 0-5 in CPSR
16 MODE_MSK DEFINE 0x1F            ; Bit mask for mode bits in CPSR
20 USR_MODE DEFINE 0x10            ; User mode
21 FIQ_MODE DEFINE 0x11            ; Fast Interrupt Request mode
22 IRQ_MODE DEFINE 0x12            ; Interrupt Request mode
23 SVC_MODE DEFINE 0x13            ; Supervisor mode
24 ABT_MODE DEFINE 0x17            ; Abort mode
25 UND_MODE DEFINE 0x1B            ; Undefined Instruction mode
26 SYS_MODE DEFINE 0x1F            ; System mode
78 ; After a reset execution starts here, the mode is ARM, supervisor
118 ; The USR mode uses the same stack as SYS.
126         BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
127         ORR     r0, r0, #IRQ_MODE       ; Set IRQ mode bits
128         MSR     cpsr_c, r0              ; Change the mode
133         BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
134         ORR     r0, r0, #FIQ_MODE       ; Set FIR mode bits
135         MSR     cpsr_c, r0              ; Change the mode
139         BIC     r0,r0,#MODE_MSK         ; Clear the mode bits
140         ORR     r0,r0,#ABT_MODE         ; Set Abort mode bits
141         MSR     cpsr_c,r0               ; Change the mode
145         BIC     r0,r0,#MODE_MSK         ; Clear the mode bits
146         ORR     r0,r0,#UND_MODE         ; Set Undefined mode bits
147         MSR     cpsr_c,r0               ; Change the mode
152         BIC     r0 ,r0, #MODE_MSK       ; Clear the mode bits
153         ORR     r0 ,r0, #SVC_MODE       ; Set System mode bits
154         MSR     cpsr_c, r0              ; Change the mode
180         MSR     cpsr_c, r1              ;/* return to Undefined Instruction mode  */
256         ; switch to SVC mode with no interrupt