Lines Matching full:clock
96 ;// <i> External Reset Time in 2^(ERSTL+1) Slow Clock Cycles
110 ;// <i> Number of Master Clock Cycles in 1us
122 ;// <i> Number of Master Clock Cycles in 1us
163 PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range
165 PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider
166 PMC_CSS EQU (3<<0) ; Clock Source Selection
170 PMC_MCKRDY EQU (1<<3) ; Master Clock Status
182 ;// <o2.14..15> OUT: PLL Clock Frequency Range
186 ;// <o2.28..29> USBDIV: USB Clock Divider
189 ;// <o3.0..1> CSS: Clock Source Selection
190 ;// <0=> Slow Clock
191 ;// <1=> Main Clock
193 ;// <3=> PLL Clock
196 ;// <1=> Clock / 2 <2=> Clock / 4
197 ;// <3=> Clock / 8 <4=> Clock / 16
198 ;// <5=> Clock / 32 <6=> Clock / 64
309 ; Select Clock
310 IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected
322 ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected
334 ENDIF ; Select Clock