Lines Matching full:clock
93 ;// <i> External Reset Time in 2^(ERSTL+1) Slow Clock Cycles
107 ;// <i> Number of Master Clock Cycles in 1us
119 ;// <i> Number of Master Clock Cycles in 1us
160 PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range
162 PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider
163 PMC_CSS EQU (3<<0) ; Clock Source Selection
167 PMC_MCKRDY EQU (1<<3) ; Master Clock Status
179 ;// <o2.14..15> OUT: PLL Clock Frequency Range
183 ;// <o2.28..29> USBDIV: USB Clock Divider
186 ;// <o3.0..1> CSS: Clock Source Selection
187 ;// <0=> Slow Clock
188 ;// <1=> Main Clock
190 ;// <3=> PLL Clock
193 ;// <1=> Clock / 2 <2=> Clock / 4
194 ;// <3=> Clock / 8 <4=> Clock / 16
195 ;// <5=> Clock / 32 <6=> Clock / 64
306 ; Select Clock
307 IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected
319 ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected
331 ENDIF ; Select Clock