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234 /* Description: Status indicating that HFCLKSTART task has been triggered */
243 /* Description: The register shows if HFXO has been requested by triggering HFCLKSTART task and if …
248 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFXO has not been started or HFCLKSTOP task has…
249 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFXO has been started (HFCLKSTARTED event has been…
257 /* Description: Status indicating that LFCLKSTART task has been triggered */
266 …he register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and …
271 …TAT_STATE_NotRunning (0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has …
272 …CLKSTAT_STATE_Running (1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has b…
282 /* Description: Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered */
326 /* Description: Status to indicate if data sent from the debugger to the CPU has been read */
342 /* Description: Status to indicate if data sent from the CPU to the debugger status has been read */
514 /* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
521 /* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
528 /* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
535 /* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
542 /* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
549 /* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
556 /* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
563 /* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
570 /* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
577 /* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
584 /* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
591 /* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
598 /* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
605 /* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
612 /* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
619 /* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
629 /* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
636 /* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
643 /* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
650 /* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
657 /* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
664 /* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
671 /* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
678 /* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
685 /* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
692 /* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
699 /* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
706 /* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
713 /* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
720 /* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
727 /* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
734 /* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
1680 /* Description: The RXD.PTR register has been copied to internal double-buffers.
1683 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers.
1700 /* Description: The TDX.PTR register has been copied to internal double-buffers.
1703 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers.
2421 /* Description: Key has been revoked and cannot be tasked for selection */
2423 /* Bit 0 : Key has been revoked and cannot be tasked for selection */
2887 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2894 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2901 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2908 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2915 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2922 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2929 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2936 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2943 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2950 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2957 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2964 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2971 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2978 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2985 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2992 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2999 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3006 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3013 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3020 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3027 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3034 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3041 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3048 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3055 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3062 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3069 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3076 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3083 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3090 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3097 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3104 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3114 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3121 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3128 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3135 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3142 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3149 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3156 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3163 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3170 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3177 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3184 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3191 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3198 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3205 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3212 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3219 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3226 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3233 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3240 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3247 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3254 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3261 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3268 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3275 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3282 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3289 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3296 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3303 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3310 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3317 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3324 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3331 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3731 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3738 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3745 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3752 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3759 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3766 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3773 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3780 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3787 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3794 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3801 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3808 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3815 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3822 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3829 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3836 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3843 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3850 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3857 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3864 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3871 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3878 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3885 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3892 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3899 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3906 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3913 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3920 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3927 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3934 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3941 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3948 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3958 …IRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3965 …IRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3972 …IRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3979 …IRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3986 …IRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3993 …IRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4000 …IRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4007 …IRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4014 …IRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4021 …IRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4028 …IRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4035 …IRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4042 …IRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4049 …IRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4056 …IRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4063 …IRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4070 …IRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4077 …IRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4084 …IRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4091 …IRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4098 …IRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4105 …IRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
4112 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4119 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4126 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4133 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4140 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4147 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4154 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4161 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4168 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4175 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4180 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to …
4183 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
4184 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
4186 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to …
4189 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
4190 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
4192 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to …
4195 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
4196 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
4198 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to …
4201 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
4202 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
4204 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to …
4207 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
4208 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
4210 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to …
4213 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
4214 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
4216 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to …
4219 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
4220 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
4222 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to …
4225 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
4226 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
4228 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to …
4231 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
4232 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
4234 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to …
4237 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
4238 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
4240 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to …
4243 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
4244 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
4246 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to …
4249 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
4250 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
4252 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to …
4255 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
4256 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
4258 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to …
4261 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
4262 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
4264 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to …
4267 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
4268 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
4270 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to …
4273 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
4274 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
4276 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to …
4279 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
4280 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
4282 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to …
4285 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
4286 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
4288 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to …
4291 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
4292 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
4294 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to …
4297 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
4298 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
4300 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to …
4303 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
4304 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
4306 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to …
4309 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
4310 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
4312 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to cle…
4315 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
4316 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
4318 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to cle…
4321 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
4322 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
4324 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to cle…
4327 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
4328 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
4330 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to cle…
4333 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
4334 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
4336 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to cle…
4339 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
4340 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
4342 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to cle…
4345 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
4346 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
4348 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to cle…
4351 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
4352 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
4354 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
4357 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
4358 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
4360 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to cle…
4363 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
4364 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
4366 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to cle…
4369 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
4370 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
4478 /* Description: PDM transfer has started */
4480 /* Bit 0 : PDM transfer has started */
4487 /* Description: PDM transfer has finished */
4489 /* Bit 0 : PDM transfer has finished */
4496 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample …
4498 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after…
5046 …n collection: Emitted at end of every sequence n, when last value from RAM has been applied to wav…
5048 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave co…
5954 /* Description: The ADC has started */
5956 /* Bit 0 : The ADC has started */
5963 /* Description: The ADC has filled up the Result buffer */
5965 /* Bit 0 : The ADC has filled up the Result buffer */
5972 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions m…
5974 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might …
5999 /* Description: The ADC has stopped */
6001 /* Bit 0 : The ADC has stopped */
6850 /* Description: SPI transaction has stopped */
6852 /* Bit 0 : SPI transaction has stopped */
7534 /* Description: A security violation has been detected for the RAM memory space */
7536 /* Bit 0 : A security violation has been detected for the RAM memory space */
7543 /* Description: A security violation has been detected for the flash memory space */
7545 /* Bit 0 : A security violation has been detected for the flash memory space */
7552 /* Description: A security violation has been detected on one or several peripherals */
7554 /* Bit 0 : A security violation has been detected on one or several peripherals */
7705 #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel15 has its non-secure attribute set */
7706 #define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel15 has its secure attribute set */
7711 #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel14 has its non-secure attribute set */
7712 #define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel14 has its secure attribute set */
7717 #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel13 has its non-secure attribute set */
7718 #define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel13 has its secure attribute set */
7723 #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel12 has its non-secure attribute set */
7724 #define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel12 has its secure attribute set */
7729 #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel11 has its non-secure attribute set */
7730 #define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel11 has its secure attribute set */
7735 #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel10 has its non-secure attribute set */
7736 #define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel10 has its secure attribute set */
7741 #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel9 has its non-secure attribute set */
7742 #define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel9 has its secure attribute set */
7747 #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel8 has its non-secure attribute set */
7748 #define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel8 has its secure attribute set */
7753 #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel7 has its non-secure attribute set */
7754 #define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel7 has its secure attribute set */
7759 #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel6 has its non-secure attribute set */
7760 #define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel6 has its secure attribute set */
7765 #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel5 has its non-secure attribute set */
7766 #define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel5 has its secure attribute set */
7771 #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel4 has its non-secure attribute set */
7772 #define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel4 has its secure attribute set */
7777 #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel3 has its non-secure attribute set */
7778 #define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel3 has its secure attribute set */
7783 #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel2 has its non-secure attribute set */
7784 #define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel2 has its secure attribute set */
7789 #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel1 has its non-secure attribute set */
7790 #define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel1 has its secure attribute set */
7795 #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel0 has its non-secure attribute set */
7796 #define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel0 has its secure attribute set */
7813 #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL) /*!< Pin 31 has its non-secure attribute set */
7814 #define SPU_GPIOPORT_PERM_PIN31_Secure (1UL) /*!< Pin 31 has its secure attribute set */
7819 #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL) /*!< Pin 30 has its non-secure attribute set */
7820 #define SPU_GPIOPORT_PERM_PIN30_Secure (1UL) /*!< Pin 30 has its secure attribute set */
7825 #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL) /*!< Pin 29 has its non-secure attribute set */
7826 #define SPU_GPIOPORT_PERM_PIN29_Secure (1UL) /*!< Pin 29 has its secure attribute set */
7831 #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL) /*!< Pin 28 has its non-secure attribute set */
7832 #define SPU_GPIOPORT_PERM_PIN28_Secure (1UL) /*!< Pin 28 has its secure attribute set */
7837 #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL) /*!< Pin 27 has its non-secure attribute set */
7838 #define SPU_GPIOPORT_PERM_PIN27_Secure (1UL) /*!< Pin 27 has its secure attribute set */
7843 #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL) /*!< Pin 26 has its non-secure attribute set */
7844 #define SPU_GPIOPORT_PERM_PIN26_Secure (1UL) /*!< Pin 26 has its secure attribute set */
7849 #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL) /*!< Pin 25 has its non-secure attribute set */
7850 #define SPU_GPIOPORT_PERM_PIN25_Secure (1UL) /*!< Pin 25 has its secure attribute set */
7855 #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL) /*!< Pin 24 has its non-secure attribute set */
7856 #define SPU_GPIOPORT_PERM_PIN24_Secure (1UL) /*!< Pin 24 has its secure attribute set */
7861 #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL) /*!< Pin 23 has its non-secure attribute set */
7862 #define SPU_GPIOPORT_PERM_PIN23_Secure (1UL) /*!< Pin 23 has its secure attribute set */
7867 #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL) /*!< Pin 22 has its non-secure attribute set */
7868 #define SPU_GPIOPORT_PERM_PIN22_Secure (1UL) /*!< Pin 22 has its secure attribute set */
7873 #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL) /*!< Pin 21 has its non-secure attribute set */
7874 #define SPU_GPIOPORT_PERM_PIN21_Secure (1UL) /*!< Pin 21 has its secure attribute set */
7879 #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL) /*!< Pin 20 has its non-secure attribute set */
7880 #define SPU_GPIOPORT_PERM_PIN20_Secure (1UL) /*!< Pin 20 has its secure attribute set */
7885 #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL) /*!< Pin 19 has its non-secure attribute set */
7886 #define SPU_GPIOPORT_PERM_PIN19_Secure (1UL) /*!< Pin 19 has its secure attribute set */
7891 #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL) /*!< Pin 18 has its non-secure attribute set */
7892 #define SPU_GPIOPORT_PERM_PIN18_Secure (1UL) /*!< Pin 18 has its secure attribute set */
7897 #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL) /*!< Pin 17 has its non-secure attribute set */
7898 #define SPU_GPIOPORT_PERM_PIN17_Secure (1UL) /*!< Pin 17 has its secure attribute set */
7903 #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL) /*!< Pin 16 has its non-secure attribute set */
7904 #define SPU_GPIOPORT_PERM_PIN16_Secure (1UL) /*!< Pin 16 has its secure attribute set */
7909 #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL) /*!< Pin 15 has its non-secure attribute set */
7910 #define SPU_GPIOPORT_PERM_PIN15_Secure (1UL) /*!< Pin 15 has its secure attribute set */
7915 #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL) /*!< Pin 14 has its non-secure attribute set */
7916 #define SPU_GPIOPORT_PERM_PIN14_Secure (1UL) /*!< Pin 14 has its secure attribute set */
7921 #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL) /*!< Pin 13 has its non-secure attribute set */
7922 #define SPU_GPIOPORT_PERM_PIN13_Secure (1UL) /*!< Pin 13 has its secure attribute set */
7927 #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL) /*!< Pin 12 has its non-secure attribute set */
7928 #define SPU_GPIOPORT_PERM_PIN12_Secure (1UL) /*!< Pin 12 has its secure attribute set */
7933 #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL) /*!< Pin 11 has its non-secure attribute set */
7934 #define SPU_GPIOPORT_PERM_PIN11_Secure (1UL) /*!< Pin 11 has its secure attribute set */
7939 #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL) /*!< Pin 10 has its non-secure attribute set */
7940 #define SPU_GPIOPORT_PERM_PIN10_Secure (1UL) /*!< Pin 10 has its secure attribute set */
7945 #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL) /*!< Pin 9 has its non-secure attribute set */
7946 #define SPU_GPIOPORT_PERM_PIN9_Secure (1UL) /*!< Pin 9 has its secure attribute set */
7951 #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL) /*!< Pin 8 has its non-secure attribute set */
7952 #define SPU_GPIOPORT_PERM_PIN8_Secure (1UL) /*!< Pin 8 has its secure attribute set */
7957 #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL) /*!< Pin 7 has its non-secure attribute set */
7958 #define SPU_GPIOPORT_PERM_PIN7_Secure (1UL) /*!< Pin 7 has its secure attribute set */
7963 #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL) /*!< Pin 6 has its non-secure attribute set */
7964 #define SPU_GPIOPORT_PERM_PIN6_Secure (1UL) /*!< Pin 6 has its secure attribute set */
7969 #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL) /*!< Pin 5 has its non-secure attribute set */
7970 #define SPU_GPIOPORT_PERM_PIN5_Secure (1UL) /*!< Pin 5 has its secure attribute set */
7975 #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL) /*!< Pin 4 has its non-secure attribute set */
7976 #define SPU_GPIOPORT_PERM_PIN4_Secure (1UL) /*!< Pin 4 has its secure attribute set */
7981 #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL) /*!< Pin 3 has its non-secure attribute set */
7982 #define SPU_GPIOPORT_PERM_PIN3_Secure (1UL) /*!< Pin 3 has its secure attribute set */
7987 #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */
7988 #define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */
7993 #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */
7994 #define SPU_GPIOPORT_PERM_PIN1_Secure (1UL) /*!< Pin 1 has its secure attribute set */
7999 #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL) /*!< Pin 0 has its non-secure attribute set */
8000 #define SPU_GPIOPORT_PERM_PIN0_Secure (1UL) /*!< Pin 0 has its secure attribute set */
8174 /* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned …
8177 #define SPU_PERIPHID_PERM_DMA_NoDMA (0UL) /*!< Peripheral has no DMA capability */
8178 #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers a…
8179 #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can…
8758 /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is …
8760 /* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now s…
9915 /* Description: UART receiver has started */
9917 /* Bit 0 : UART receiver has started */
9924 /* Description: UART transmitter has started */
9926 /* Bit 0 : UART transmitter has started */