Lines Matching full:enabled

191 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
198 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
208 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
215 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
312 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */
362 /* Bits 31..0 : Initiate secure erase even though ERASEPROTECT is enabled if KEY fields match */
518 #define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
525 #define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
532 #define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
539 #define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
546 #define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
553 #define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
560 #define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
567 #define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
574 #define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
581 #define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
588 #define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
595 #define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
602 #define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
609 #define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
616 #define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
623 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
633 #define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
640 #define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
647 #define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
654 #define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
661 #define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
668 #define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
675 #define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
682 #define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
689 #define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
696 #define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
703 #define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
710 #define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
717 #define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
724 #define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
731 #define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
738 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
742 … group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG[n].EN/DIS are enabled. */
993 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1000 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1007 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1014 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1021 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1028 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1035 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1042 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1049 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1056 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1063 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1070 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1077 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1084 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1091 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1098 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1108 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1115 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1122 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1129 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1136 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1143 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1150 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1157 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1164 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1171 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1178 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1185 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1192 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1199 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1206 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1213 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1439 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1441 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1480 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1487 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1494 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1501 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1508 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1515 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1522 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1529 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1536 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1546 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1553 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1560 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1567 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1574 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
1581 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
1588 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
1595 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
1602 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
1638 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
1640 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
1681 …When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAX…
1684 …When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAX…
1701 …When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAX…
1704 …When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAX…
1777 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1784 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1791 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1801 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1808 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1815 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1843 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
1852 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2028 /* Description: Description collection: Trigger events on channel enabled in SEND_CNF[n]. */
2030 /* Bit 0 : Trigger events on channel enabled in SEND_CNF[n]. */
2049 /* Description: Description collection: Event received on one or more of the enabled channels in RE…
2051 /* Bit 0 : Event received on one or more of the enabled channels in RECEIVE_CNF[n]. */
2128 #define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2135 #define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2142 #define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2149 #define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2156 #define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2163 #define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2170 #define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2177 #define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2187 #define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2194 #define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2201 #define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2208 #define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2215 #define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2222 #define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2229 #define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2236 #define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2466 #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2473 #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2480 #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2490 #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2497 #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2504 #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2579 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
2580 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
2581 #define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */
2586 … non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG…
2635 #define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */
2636 #define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */
4571 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
4578 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4585 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4595 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
4602 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4609 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4858 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4865 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4872 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4882 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4889 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4896 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4973 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequ…
4975 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing th…
4981 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=…
4983 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextS…
5222 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5229 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5236 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5243 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5250 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5257 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5264 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5274 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5281 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5288 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5295 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5302 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5309 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5316 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5469 #define REGULATORS_DCDCEN_DCDCEN_Enabled (1UL) /*!< DC/DC mode is enabled */
5632 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5639 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5646 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5653 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5660 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5667 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5677 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5684 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5691 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5698 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5705 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5712 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5761 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5768 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5775 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5782 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5789 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5796 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5806 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5813 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5820 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5827 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5834 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5841 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5878 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */
5880 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
6271 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6278 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6285 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6292 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6299 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6306 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6313 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6320 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6327 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6334 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6341 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6348 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6355 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6362 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6369 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6376 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6383 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6390 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6397 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6404 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
6411 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6418 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6428 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6435 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6442 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6449 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6456 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6463 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6470 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6477 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6484 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6491 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6498 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6505 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6512 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6519 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6526 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6533 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6540 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6547 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6554 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6561 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
6568 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6575 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6637 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
6975 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6982 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
6989 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6996 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7003 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7013 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7020 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7027 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7034 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7041 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7322 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7329 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7336 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7346 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7353 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7360 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7627 #define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7634 #define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7641 #define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
7651 #define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7658 #define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7665 #define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
8512 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8519 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8526 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8533 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8540 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8547 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8557 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8564 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8571 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8578 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8585 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8592 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8984 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8991 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
8998 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9005 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9012 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9019 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9026 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9036 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
9043 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
9050 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9057 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9064 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9071 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9078 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9516 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
9523 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
9530 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9537 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9544 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9551 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9561 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
9568 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
9575 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9582 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9589 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9596 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9718 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
9724 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
10175 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10182 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10189 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10196 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
10203 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10210 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10217 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10224 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10231 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10238 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
10245 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
10255 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10262 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10269 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10276 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
10283 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10290 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10297 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10304 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10311 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10318 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
10325 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
10502 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
10586 …E_Active (1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */
10591 …Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */
10808 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10818 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10836 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are alre…
10837 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not y…
10842 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are alre…
10843 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not y…
10848 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are alre…
10849 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not y…
10854 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are alre…
10855 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not y…
10860 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are alre…
10861 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not y…
10866 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are alre…
10867 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
10872 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are alre…
10873 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not y…
10878 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are alre…
10879 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not y…