Lines Matching full:bits

82 /* Bits 3..0 : Channel that task HFCLKSTART will subscribe to */
95 /* Bits 3..0 : Channel that task HFCLKSTOP will subscribe to */
108 /* Bits 3..0 : Channel that task LFCLKSTART will subscribe to */
121 /* Bits 3..0 : Channel that task LFCLKSTOP will subscribe to */
152 /* Bits 3..0 : Channel that event HFCLKSTARTED will publish to. */
165 /* Bits 3..0 : Channel that event LFCLKSTARTED will publish to. */
274 /* Bits 1..0 : Active clock source */
284 /* Bits 1..0 : Clock source */
294 /* Bits 1..0 : Clock source */
321 /* Bits 31..0 : Data received from debugger */
337 /* Bits 31..0 : Data sent to debugger */
362 /* Bits 31..0 : Initiate secure erase even though ERASEPROTECT is enabled if KEY fields match */
395 /* Bits 3..0 : Channel that task CHG[n].EN will subscribe to */
408 /* Bits 3..0 : Channel that task CHG[n].DIS will subscribe to */
861 /* Bits 3..0 : Channel that task TRIGGER[n] will subscribe to */
883 /* Bits 3..0 : Channel that event TRIGGERED[n] will publish to. */
1223 /* Bits 31..0 : 64 bit unique device identifier */
1230 /* Bits 31..0 : Part code */
1238 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
1247 /* Bits 31..0 : Package option */
1255 /* Bits 31..0 : RAM variant */
1264 /* Bits 31..0 : Flash variant */
1272 /* Bits 31..0 : Code memory page size */
1279 /* Bits 31..0 : Code memory size in number of pages */
1286 /* Bits 31..0 : Device type */
1295 /* Bits 31..0 : Address */
1302 /* Bits 31..0 : Data */
1307 /* Description: Amount of bytes for the required entropy bits */
1309 /* Bits 31..0 : Amount of bytes for the required entropy bits */
1316 /* Bits 31..0 : Repetition counter cutoff */
1323 /* Bits 31..0 : Adaptive proportion cutoff */
1330 /* Bits 31..0 : Amount of bytes for the startup tests */
1337 /* Bits 31..0 : Sample count for ring oscillator 1 */
1344 /* Bits 31..0 : Sample count for ring oscillator 2 */
1351 /* Bits 31..0 : Sample count for ring oscillator 3 */
1358 /* Bits 31..0 : Sample count for ring oscillator 4 */
1399 /* Bits 3..0 : Channel that task OUT[n] will subscribe to */
1412 /* Bits 3..0 : Channel that task SET[n] will subscribe to */
1425 /* Bits 3..0 : Channel that task CLR[n] will subscribe to */
1456 /* Bits 3..0 : Channel that event IN[n] will publish to. */
1469 /* Bits 3..0 : Channel that event PORT will publish to. */
1614 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is trigger…
1622 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
1626 /* Bits 1..0 : Mode */
1662 /* Bits 3..0 : Channel that task START will subscribe to */
1675 /* Bits 3..0 : Channel that task STOP will subscribe to */
1719 /* Bits 3..0 : Channel that event RXPTRUPD will publish to. */
1732 /* Bits 3..0 : Channel that event STOPPED will publish to. */
1745 /* Bits 3..0 : Channel that event TXPTRUPD will publish to. */
1866 /* Bits 31..0 : Master clock generator frequency. */
1886 /* Bits 3..0 : MCK / LRCK ratio. */
1902 /* Bits 1..0 : Sample width. */
1930 /* Bits 1..0 : Enable channels. */
1940 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples wil…
1947 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples…
1954 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
1967 /* Bits 4..0 : Pin number */
1980 /* Bits 4..0 : Pin number */
1993 /* Bits 4..0 : Pin number */
2006 /* Bits 4..0 : Pin number */
2019 /* Bits 4..0 : Pin number */
2044 /* Bits 3..0 : Channel that task SEND[n] will subscribe to */
2066 /* Bits 3..0 : Channel that event RECEIVE[n] will publish to. */
2395 /* Bits 31..0 : General purpose memory */
2529 /* Description: Status bits for KMU operation */
2546 /* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_K…
2575 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and wr…
2595 /* Bits 6..0 : Duration of the partial erase in milliseconds */
2617 /* Bits 31..0 : Number of cache hits */
2624 /* Bits 31..0 : Number of cache misses */
2631 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and wr…
2641 /* Bits 31..4 : Key to write in order to validate the write operation */
2663 /* Bits 31..8 : KEY */
2666 …VM_KEY_EnableWrite (0xACCE55UL) /*!< Must be written in order to write to bits 0-7. Any other valu…
2880 /* Description: Set individual bits in GPIO port */
3107 /* Description: Clear individual bits in GPIO port */
4393 /* Bits 17..16 : Pin sensing mechanism */
4400 /* Bits 10..8 : Drive configuration */
4412 /* Bits 3..2 : Pull configuration */
4460 /* Bits 3..0 : Channel that task START will subscribe to */
4473 /* Bits 3..0 : Channel that task STOP will subscribe to */
4513 /* Bits 3..0 : Channel that event STARTED will publish to. */
4526 /* Bits 3..0 : Channel that event STOPPED will publish to. */
4539 /* Bits 3..0 : Channel that event END will publish to. */
4624 /* Bits 31..0 : PDM_CLK frequency */
4652 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see el…
4662 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see e…
4687 /* Bits 4..0 : Pin number */
4700 /* Bits 4..0 : Pin number */
4707 /* Bits 31..0 : Address to write PDM samples to over DMA */
4714 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
4747 /* Bits 3..0 : Channel that task CONSTLAT will subscribe to */
4760 /* Bits 3..0 : Channel that task LOWPWR will subscribe to */
4800 /* Bits 3..0 : Channel that event POFWARN will publish to. */
4813 /* Bits 3..0 : Channel that event SLEEPENTER will publish to. */
4826 /* Bits 3..0 : Channel that event SLEEPEXIT will publish to. */
4956 /* Bits 7..0 : General purpose retention register */
4997 /* Bits 3..0 : Channel that task STOP will subscribe to */
5010 /* Bits 3..0 : Channel that task SEQSTART[n] will subscribe to */
5023 /* Bits 3..0 : Channel that task NEXTSTEP will subscribe to */
5081 /* Bits 3..0 : Channel that event STOPPED will publish to. */
5094 /* Bits 3..0 : Channel that event SEQSTARTED[n] will publish to. */
5107 /* Bits 3..0 : Channel that event SEQEND[n] will publish to. */
5120 /* Bits 3..0 : Channel that event PWMPERIODEND will publish to. */
5133 /* Bits 3..0 : Channel that event LOOPSDONE will publish to. */
5340 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when…
5347 /* Bits 2..0 : Prescaler of PWM_CLK */
5368 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
5379 /* Bits 15..0 : Number of playbacks of pattern cycles */
5387 /* Bits 31..0 : Beginning address in RAM of this sequence */
5394 /* Bits 14..0 : Number of values (duty cycles) in this sequence */
5402 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load…
5410 /* Bits 23..0 : Time added after the sequence in PWM periods */
5423 /* Bits 4..0 : Pin number */
5442 /* Bits 4..1 : Power-fail comparator threshold setting */
5516 /* Bits 3..0 : Channel that task START will subscribe to */
5529 /* Bits 3..0 : Channel that task STOP will subscribe to */
5542 /* Bits 3..0 : Channel that task CLEAR will subscribe to */
5555 /* Bits 3..0 : Channel that task TRIGOVRFLW will subscribe to */
5595 /* Bits 3..0 : Channel that event TICK will publish to. */
5608 /* Bits 3..0 : Channel that event OVRFLW will publish to. */
5621 /* Bits 3..0 : Channel that event COMPARE[n] will publish to. */
5847 /* Bits 23..0 : Counter value */
5854 /* Bits 11..0 : Prescaler value */
5861 /* Bits 23..0 : Compare value */
5910 /* Bits 3..0 : Channel that task START will subscribe to */
5923 /* Bits 3..0 : Channel that task SAMPLE will subscribe to */
5936 /* Bits 3..0 : Channel that task STOP will subscribe to */
5949 /* Bits 3..0 : Channel that task CALIBRATEOFFSET will subscribe to */
6034 /* Bits 3..0 : Channel that event STARTED will publish to. */
6047 /* Bits 3..0 : Channel that event END will publish to. */
6060 /* Bits 3..0 : Channel that event DONE will publish to. */
6073 /* Bits 3..0 : Channel that event RESULTDONE will publish to. */
6086 /* Bits 3..0 : Channel that event CALIBRATEDONE will publish to. */
6099 /* Bits 3..0 : Channel that event STOPPED will publish to. */
6112 /* Bits 3..0 : Channel that event CH[n].LIMITH will publish to. */
6125 /* Bits 3..0 : Channel that event CH[n].LIMITL will publish to. */
6599 /* Bits 4..0 : Analog positive input channel */
6616 /* Bits 4..0 : Analog negative input, enables differential channel */
6645 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
6661 /* Bits 10..8 : Gain control */
6673 /* Bits 5..4 : Negative channel resistor control */
6681 /* Bits 1..0 : Positive channel resistor control */
6692 /* Bits 31..16 : High level limit */
6696 /* Bits 15..0 : Low level limit */
6703 /* Bits 2..0 : Set the resolution */
6714 /* Bits 3..0 : Oversample control */
6736 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
6743 /* Bits 31..0 : Data pointer */
6750 /* Bits 14..0 : Maximum number of buffer words to transfer */
6757 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read afte…
6806 /* Bits 3..0 : Channel that task START will subscribe to */
6819 /* Bits 3..0 : Channel that task STOP will subscribe to */
6832 /* Bits 3..0 : Channel that task SUSPEND will subscribe to */
6845 /* Bits 3..0 : Channel that task RESUME will subscribe to */
6903 /* Bits 3..0 : Channel that event STOPPED will publish to. */
6916 /* Bits 3..0 : Channel that event ENDRX will publish to. */
6929 /* Bits 3..0 : Channel that event END will publish to. */
6942 /* Bits 3..0 : Channel that event ENDTX will publish to. */
6955 /* Bits 3..0 : Channel that event STARTED will publish to. */
7047 /* Bits 3..0 : Enable or disable SPIM */
7062 /* Bits 4..0 : Pin number */
7075 /* Bits 4..0 : Pin number */
7088 /* Bits 4..0 : Pin number */
7095 /* Bits 31..0 : SPI master data rate */
7109 /* Bits 31..0 : Data pointer */
7116 /* Bits 12..0 : Maximum number of bytes in receive buffer */
7123 /* Bits 12..0 : Number of bytes transferred in the last transaction */
7130 /* Bits 1..0 : List type */
7139 /* Bits 31..0 : Data pointer */
7146 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
7153 /* Bits 12..0 : Number of bytes transferred in the last transaction */
7160 /* Bits 1..0 : List type */
7190 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. …
7223 /* Bits 3..0 : Channel that task ACQUIRE will subscribe to */
7236 /* Bits 3..0 : Channel that task RELEASE will subscribe to */
7276 /* Bits 3..0 : Channel that event END will publish to. */
7289 /* Bits 3..0 : Channel that event ENDRX will publish to. */
7302 /* Bits 3..0 : Channel that event ACQUIRED will publish to. */
7366 /* Bits 1..0 : Semaphore status */
7394 /* Bits 3..0 : Enable or disable SPI slave */
7409 /* Bits 4..0 : Pin number */
7422 /* Bits 4..0 : Pin number */
7435 /* Bits 4..0 : Pin number */
7448 /* Bits 4..0 : Pin number */
7455 /* Bits 31..0 : RXD data pointer */
7462 /* Bits 12..0 : Maximum number of bytes in receive buffer */
7469 /* Bits 12..0 : Number of bytes received in the last granted transaction */
7476 /* Bits 31..0 : TXD data pointer */
7483 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
7490 /* Bits 12..0 : Number of bytes transmitted in last granted transaction */
7518 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
7525 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer…
7569 /* Bits 3..0 : Channel that event RAMACCERR will publish to. */
7582 /* Bits 3..0 : Channel that event FLASHACCERR will publish to. */
7595 /* Bits 3..0 : Channel that event PERIPHACCERR will publish to. */
7692 /* Bits 1..0 : Define configuration capabilities  for TrustZone Cortex-M secure attribute */
8020 /* Bits 4..0 : Region number */
8033 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
8055 /* Bits 3..0 : Region number */
8068 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */
8174 /* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned …
8181 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
8211 /* Bits 4..0 : Pin number */
8224 /* Bits 4..0 : Pin number */
8237 /* Bits 4..0 : Pin number */
8250 /* Bits 4..0 : Pin number */
8263 /* Bits 4..0 : Pin number */
8270 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided…
8339 /* Bits 3..0 : Channel that task START will subscribe to */
8352 /* Bits 3..0 : Channel that task STOP will subscribe to */
8365 /* Bits 3..0 : Channel that task COUNT will subscribe to */
8378 /* Bits 3..0 : Channel that task CLEAR will subscribe to */
8391 /* Bits 3..0 : Channel that task SHUTDOWN will subscribe to */
8404 /* Bits 3..0 : Channel that task CAPTURE[n] will subscribe to */
8426 /* Bits 3..0 : Channel that event COMPARE[n] will publish to. */
8598 /* Bits 1..0 : Timer mode */
8606 /* Description: Configure the number of bits used by the TIMER */
8608 /* Bits 1..0 : Timer bit width */
8619 /* Bits 3..0 : Prescaler value */
8626 /* Bits 31..0 : Capture/Compare value */
8683 /* Bits 3..0 : Channel that task STARTRX will subscribe to */
8696 /* Bits 3..0 : Channel that task STARTTX will subscribe to */
8709 /* Bits 3..0 : Channel that task STOP will subscribe to */
8722 /* Bits 3..0 : Channel that task SUSPEND will subscribe to */
8735 /* Bits 3..0 : Channel that task RESUME will subscribe to */
8811 /* Bits 3..0 : Channel that event STOPPED will publish to. */
8824 /* Bits 3..0 : Channel that event ERROR will publish to. */
8837 /* Bits 3..0 : Channel that event SUSPENDED will publish to. */
8850 /* Bits 3..0 : Channel that event RXSTARTED will publish to. */
8863 /* Bits 3..0 : Channel that event TXSTARTED will publish to. */
8876 /* Bits 3..0 : Channel that event LASTRX will publish to. */
8889 /* Bits 3..0 : Channel that event LASTTX will publish to. */
9105 /* Bits 3..0 : Enable or disable TWIM */
9120 /* Bits 4..0 : Pin number */
9133 /* Bits 4..0 : Pin number */
9140 /* Bits 31..0 : TWI master clock frequency */
9150 /* Bits 31..0 : Data pointer */
9157 /* Bits 12..0 : Maximum number of bytes in receive buffer */
9164 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, include…
9171 /* Bits 1..0 : List type */
9180 /* Bits 31..0 : Data pointer */
9187 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
9194 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, include…
9201 /* Bits 1..0 : List type */
9210 /* Bits 6..0 : Address used in the TWI transfer */
9267 /* Bits 3..0 : Channel that task STOP will subscribe to */
9280 /* Bits 3..0 : Channel that task SUSPEND will subscribe to */
9293 /* Bits 3..0 : Channel that task RESUME will subscribe to */
9306 /* Bits 3..0 : Channel that task PREPARERX will subscribe to */
9319 /* Bits 3..0 : Channel that task PREPARETX will subscribe to */
9386 /* Bits 3..0 : Channel that event STOPPED will publish to. */
9399 /* Bits 3..0 : Channel that event ERROR will publish to. */
9412 /* Bits 3..0 : Channel that event RXSTARTED will publish to. */
9425 /* Bits 3..0 : Channel that event TXSTARTED will publish to. */
9438 /* Bits 3..0 : Channel that event WRITE will publish to. */
9451 /* Bits 3..0 : Channel that event READ will publish to. */
9630 /* Bits 3..0 : Enable or disable TWIS */
9645 /* Bits 4..0 : Pin number */
9658 /* Bits 4..0 : Pin number */
9665 /* Bits 31..0 : RXD Data pointer */
9672 /* Bits 12..0 : Maximum number of bytes in RXD buffer */
9679 /* Bits 12..0 : Number of bytes transferred in the last RXD transaction */
9686 /* Bits 31..0 : TXD Data pointer */
9693 /* Bits 12..0 : Maximum number of bytes in TXD buffer */
9700 /* Bits 12..0 : Number of bytes transferred in the last TXD transaction */
9707 /* Bits 6..0 : TWI slave address */
9729 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buff…
9786 /* Bits 3..0 : Channel that task STARTRX will subscribe to */
9799 /* Bits 3..0 : Channel that task STOPRX will subscribe to */
9812 /* Bits 3..0 : Channel that task STARTTX will subscribe to */
9825 /* Bits 3..0 : Channel that task STOPTX will subscribe to */
9838 /* Bits 3..0 : Channel that task FLUSHRX will subscribe to */
9950 /* Bits 3..0 : Channel that event CTS will publish to. */
9963 /* Bits 3..0 : Channel that event NCTS will publish to. */
9976 /* Bits 3..0 : Channel that event RXDRDY will publish to. */
9989 /* Bits 3..0 : Channel that event ENDRX will publish to. */
10002 /* Bits 3..0 : Channel that event TXDRDY will publish to. */
10015 /* Bits 3..0 : Channel that event ENDTX will publish to. */
10028 /* Bits 3..0 : Channel that event ERROR will publish to. */
10041 /* Bits 3..0 : Channel that event RXTO will publish to. */
10054 /* Bits 3..0 : Channel that event RXSTARTED will publish to. */
10067 /* Bits 3..0 : Channel that event TXSTARTED will publish to. */
10080 /* Bits 3..0 : Channel that event TXSTOPPED will publish to. */
10358 /* Bits 3..0 : Enable or disable UARTE */
10373 /* Bits 4..0 : Pin number */
10386 /* Bits 4..0 : Pin number */
10399 /* Bits 4..0 : Pin number */
10412 /* Bits 4..0 : Pin number */
10419 /* Bits 31..0 : Baud rate */
10444 /* Bits 31..0 : Data pointer */
10451 /* Bits 12..0 : Maximum number of bytes in receive buffer */
10458 /* Bits 12..0 : Number of bytes transferred in the last transaction */
10465 /* Bits 31..0 : Data pointer */
10472 /* Bits 12..0 : Maximum number of bytes in transmit buffer */
10479 /* Bits 12..0 : Number of bytes transferred in the last transaction */
10486 /* Bit 4 : Stop bits */
10490 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
10492 /* Bits 3..1 : Parity */
10511 /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and
10521 /* Bits 5..0 : Pierce current DAC control signals */
10537 /* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */
10546 /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure
10556 /* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality */
10563 /* Description: Description collection: OTP bits [31+n*32:0+n*32]. */
10565 /* Bits 31..0 : Bits [31+n*32:0+n*32] of OTP region */
10575 /* Bits 31..0 : Secure APB destination address */
10580 /* Description: Description cluster: Define permissions for the key slot with ID=n+1. Bits 0-15 and…
10607 /* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key s…
10609 /* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot ID=n+1 */
10775 /* Bits 3..0 : Channel that task START will subscribe to */
10797 /* Bits 3..0 : Channel that event TIMEOUT will publish to. */
10884 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
10957 /* Bits 31..0 : Reload request register */