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8 1. Redistributions of source code must retain the above copyright notice, this
47 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
55 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
63 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
71 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
80 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
93 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
106 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
119 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
132 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
141 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
150 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
163 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
172 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
173 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
176 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */
182 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */
187 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
188 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
191 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
192 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
194 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
198 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
199 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
204 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
205 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
208 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
209 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
211 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
215 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
216 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
221 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
222 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
225 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
231 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
240 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
249 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFXO has been started (HFCLKSTARTED event has been…
254 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crysta…
263 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
272 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< Requested LFCLK source has been started (LFCLKSTAR…
274 /* Bits 1..0 : Active clock source */
278 #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
284 /* Bits 1..0 : Clock source */
288 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
294 /* Bits 1..0 : Clock source */
298 #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
312 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */
332 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA…
348 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA…
357 #define CTRLAPPERI_ERASEPROTECT_LOCK_ERASEPROTECTLOCK_Locked (1UL) /*!< ERASEALL is locked */
376 #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
384 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
393 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */
406 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */
419 #define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
425 #define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
431 #define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
437 #define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
443 #define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
449 #define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
455 #define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
461 #define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
467 #define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
473 #define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
479 #define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
485 #define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
491 #define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
497 #define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
499 /* Bit 1 : Enable or disable channel 1 */
500 #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
503 #define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
509 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
518 #define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
519 #define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
525 #define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
526 #define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
532 #define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
533 #define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
539 #define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
540 #define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
546 #define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
547 #define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
553 #define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
554 #define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
560 #define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
561 #define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
567 #define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
568 #define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
574 #define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
575 #define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
581 #define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
582 #define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
588 #define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
589 #define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
595 #define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
596 #define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
602 #define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
603 #define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
609 #define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
610 #define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
612 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
613 #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
616 #define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
617 #define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
623 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
624 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
633 #define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
634 #define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
640 #define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
641 #define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
647 #define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
648 #define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
654 #define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
655 #define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
661 #define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
662 #define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
668 #define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
669 #define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
675 #define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
676 #define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
682 #define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
683 #define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
689 #define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
690 #define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
696 #define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
697 #define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
703 #define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
704 #define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
710 #define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
711 #define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
717 #define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
718 #define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
724 #define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
725 #define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
727 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
728 #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
731 #define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
732 #define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
738 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
739 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
748 #define DPPIC_CHG_CH15_Included (1UL) /*!< Include */
754 #define DPPIC_CHG_CH14_Included (1UL) /*!< Include */
760 #define DPPIC_CHG_CH13_Included (1UL) /*!< Include */
766 #define DPPIC_CHG_CH12_Included (1UL) /*!< Include */
772 #define DPPIC_CHG_CH11_Included (1UL) /*!< Include */
778 #define DPPIC_CHG_CH10_Included (1UL) /*!< Include */
784 #define DPPIC_CHG_CH9_Included (1UL) /*!< Include */
790 #define DPPIC_CHG_CH8_Included (1UL) /*!< Include */
796 #define DPPIC_CHG_CH7_Included (1UL) /*!< Include */
802 #define DPPIC_CHG_CH6_Included (1UL) /*!< Include */
808 #define DPPIC_CHG_CH5_Included (1UL) /*!< Include */
814 #define DPPIC_CHG_CH4_Included (1UL) /*!< Include */
820 #define DPPIC_CHG_CH3_Included (1UL) /*!< Include */
826 #define DPPIC_CHG_CH2_Included (1UL) /*!< Include */
828 /* Bit 1 : Include or exclude channel 1 */
829 #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
832 #define DPPIC_CHG_CH1_Included (1UL) /*!< Include */
838 #define DPPIC_CHG_CH0_Included (1UL) /*!< Include */
850 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
859 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */
872 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
881 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */
894 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
900 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
906 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
912 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
918 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
924 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
930 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
936 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
942 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
948 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
954 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
960 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
966 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
972 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
974 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
975 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
978 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
984 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
989 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
993 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
994 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
996 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
1000 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1001 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1003 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
1007 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1008 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1010 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
1014 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1015 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1017 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
1021 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1022 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1024 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
1028 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1029 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1031 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
1035 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1036 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1038 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
1042 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1043 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1045 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
1049 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1050 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1052 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
1056 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1057 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1059 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
1063 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1064 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1066 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
1070 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1071 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1073 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
1077 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1078 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1080 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
1084 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1085 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1087 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
1088 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1091 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1092 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1094 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
1098 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1099 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1104 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
1108 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1109 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1111 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
1115 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1116 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1118 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
1122 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1123 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1125 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
1129 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1130 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1132 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
1136 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1137 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1139 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
1143 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1144 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1146 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
1150 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1151 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1153 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
1157 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1158 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1160 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
1164 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1165 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1167 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
1171 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1172 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1174 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
1178 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1179 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1181 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
1185 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1186 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1188 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
1192 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1193 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1195 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
1199 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1200 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1202 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
1203 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1206 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1207 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1209 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
1213 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1214 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1267 #define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
1335 /* Description: Sample count for ring oscillator 1 */
1337 /* Bits 31..0 : Sample count for ring oscillator 1 */
1372 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
1380 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
1388 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
1397 #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */
1410 #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */
1423 #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */
1436 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
1445 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
1454 #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */
1467 #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */
1476 /* Bit 31 : Write '1' to enable interrupt for event PORT */
1480 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1481 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
1483 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
1487 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1488 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
1490 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
1494 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1495 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
1497 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
1501 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1502 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
1504 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
1508 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1509 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
1511 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
1515 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1516 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
1518 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
1522 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1523 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
1525 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
1526 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
1529 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1530 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
1532 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
1536 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1537 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
1542 /* Bit 31 : Write '1' to disable interrupt for event PORT */
1546 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1547 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
1549 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
1553 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1554 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
1556 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
1560 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1561 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
1563 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
1567 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1568 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
1570 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
1574 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
1575 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
1577 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
1581 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
1582 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
1584 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
1588 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
1589 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
1591 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
1592 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
1595 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
1596 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
1598 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
1602 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
1603 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
1612 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggerin…
1618 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: G…
1626 /* Bits 1..0 : Mode */
1630 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
1643 #define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
1651 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
1660 #define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
1673 #define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
1688 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */
1697 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
1708 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */
1717 #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
1730 #define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
1743 #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */
1756 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
1762 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
1764 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */
1765 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
1768 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
1773 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
1777 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1778 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
1780 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */
1784 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1785 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
1787 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
1788 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
1791 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1792 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
1797 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
1801 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1802 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
1804 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */
1808 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
1809 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
1811 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
1812 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
1815 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
1816 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
1825 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
1834 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master…
1843 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
1852 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
1861 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on …
1890 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
1902 /* Bits 1..0 : Sample width. */
1906 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
1916 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
1925 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
1930 /* Bits 1..0 : Enable channels. */
1934 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
1965 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
1978 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
1991 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2004 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2017 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
2033 #define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */
2042 #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */
2055 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL) /*!< Event generated */
2064 #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */
2077 #define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */
2083 #define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */
2089 #define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */
2095 #define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */
2101 #define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */
2107 #define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */
2109 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
2110 #define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2113 #define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */
2119 #define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */
2124 /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
2128 #define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2129 #define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */
2131 /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
2135 #define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2136 #define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */
2138 /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
2142 #define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2143 #define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */
2145 /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
2149 #define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2150 #define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */
2152 /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
2156 #define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2157 #define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */
2159 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
2163 #define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2164 #define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */
2166 /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
2167 #define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2170 #define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2171 #define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */
2173 /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
2177 #define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2178 #define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */
2183 /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
2187 #define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */
2188 #define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */
2190 /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
2194 #define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */
2195 #define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */
2197 /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
2201 #define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */
2202 #define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */
2204 /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
2208 #define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */
2209 #define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */
2211 /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
2215 #define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */
2216 #define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */
2218 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
2222 #define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */
2223 #define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */
2225 /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
2226 #define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2229 #define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */
2230 #define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */
2232 /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
2236 #define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */
2237 #define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */
2246 #define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */
2252 #define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */
2258 #define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */
2264 #define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */
2270 #define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */
2276 #define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */
2278 /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
2279 #define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */
2282 #define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */
2288 #define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */
2297 #define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast. */
2303 #define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast. */
2309 #define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast. */
2315 #define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast. */
2321 #define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast. */
2327 #define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast. */
2329 /* Bit 1 : Enable broadcasting on channel 1. */
2330 #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
2333 #define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast. */
2339 #define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast. */
2348 #define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events. */
2354 #define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events. */
2360 #define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events. */
2366 #define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events. */
2372 #define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events. */
2378 #define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events. */
2380 /* Bit 1 : Enable subscription to channel 1. */
2381 #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */
2384 #define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events. */
2390 #define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events. */
2409 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL) /*!< Trigger task */
2418 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL) /*!< Event generated */
2427 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL) /*!< Event generated */
2436 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL) /*!< Event generated */
2445 #define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL) /*!< Enable */
2447 /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */
2448 #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2451 #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL) /*!< Enable */
2457 #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL) /*!< Enable */
2462 /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */
2466 #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2467 #define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL) /*!< Enable */
2469 /* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */
2470 #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2473 #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2474 #define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL) /*!< Enable */
2476 /* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */
2480 #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2481 #define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL) /*!< Enable */
2486 /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */
2490 #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */
2491 #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL) /*!< Disable */
2493 /* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */
2494 #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2497 #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */
2498 #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL) /*!< Disable */
2500 /* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */
2504 #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */
2505 #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL) /*!< Disable */
2514 #define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL) /*!< Read: Pending */
2516 /* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */
2517 #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */
2520 #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL) /*!< Read: Pending */
2526 #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL) /*!< Read: Pending */
2531 /* Bit 1 : Violation status */
2532 #define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */
2535 #define KMU_STATUS_BLOCKED_Enabled (1UL) /*!< Access violation detected and blocked */
2541 #define KMU_STATUS_SELECTED_Enabled (1UL) /*!< Key slot ID successfully selected by KMU */
2546 …ex N in UICR-&gt;KEYSLOT.KEY[N] and UICR-&gt;KEYSLOT.CONFIG[N] corresponds to KMU keyslot ID=N+1 */
2561 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
2570 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
2579 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
2590 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
2606 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
2612 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
2631 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and wr…
2635 #define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */
2649 #define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */
2658 #define NVMC_FORCEONNVM_FORCEONNVM_ForceOn (1UL) /*!< Force on NVM supply */
2668 /* Bit 1 : Force off NVM supply 1. Also see the internal section in the NVMC chapter. */
2669 #define NVMC_FORCEOFFNVM_FORCEOFFNVM1_Pos (1UL) /*!< Position of FORCEOFFNVM1 field. */
2672 #define NVMC_FORCEOFFNVM_FORCEOFFNVM1_ForceOff (1UL) /*!< Force off supply */
2678 #define NVMC_FORCEOFFNVM_FORCEOFFNVM0_ForceOff (1UL) /*!< Force off supply */
2691 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
2697 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
2703 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
2709 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
2715 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
2721 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
2727 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
2733 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
2739 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
2745 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
2751 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
2757 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
2763 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
2769 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
2775 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
2781 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
2787 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
2793 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
2799 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
2805 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
2811 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
2817 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
2823 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
2829 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
2835 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
2841 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
2847 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
2853 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
2859 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
2865 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
2867 /* Bit 1 : Pin 1 */
2868 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2871 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
2877 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
2886 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
2887 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2893 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
2894 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2900 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
2901 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2907 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
2908 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2914 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
2915 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2921 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
2922 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2928 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
2929 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2935 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
2936 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2942 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
2943 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2949 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
2950 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2956 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
2957 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2963 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
2964 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2970 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
2971 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2977 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
2978 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2984 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
2985 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2991 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
2992 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
2998 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
2999 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3005 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
3006 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3012 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
3013 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3019 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
3020 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3026 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
3027 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3033 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
3034 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
3040 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
3041 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3047 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
3048 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3054 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
3055 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3061 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
3062 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3068 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
3069 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3075 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
3076 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3082 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
3083 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3089 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
3090 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3092 /* Bit 1 : Pin 1 */
3093 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3096 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
3097 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3103 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
3104 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
3113 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
3114 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3120 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
3121 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3127 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
3128 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3134 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
3135 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3141 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
3142 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3148 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
3149 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3155 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
3156 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3162 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
3163 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3169 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
3170 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3176 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
3177 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3183 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
3184 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3190 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
3191 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3197 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
3198 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3204 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
3205 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3211 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
3212 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3218 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
3219 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3225 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
3226 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3232 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
3233 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3239 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
3240 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3246 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
3247 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3253 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
3254 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3260 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
3261 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
3267 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
3268 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3274 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
3275 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3281 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
3282 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3288 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
3289 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3295 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
3296 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3302 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
3303 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3309 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
3310 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3316 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
3317 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3319 /* Bit 1 : Pin 1 */
3320 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3323 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
3324 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3330 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
3331 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
3340 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
3346 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
3352 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
3358 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
3364 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
3370 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
3376 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
3382 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
3388 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
3394 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
3400 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
3406 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
3412 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
3418 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
3424 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
3430 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
3436 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
3442 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
3448 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
3454 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
3460 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
3466 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
3472 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
3478 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
3484 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
3490 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
3496 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
3502 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
3508 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
3514 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
3516 /* Bit 1 : Pin 1 */
3517 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3520 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
3526 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
3535 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
3541 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
3547 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
3553 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
3559 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
3565 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
3571 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
3577 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
3583 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
3589 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
3595 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
3601 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
3607 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
3613 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
3619 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
3625 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
3631 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
3637 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
3643 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
3649 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
3655 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
3661 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
3667 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
3673 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
3679 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
3685 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
3691 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
3697 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
3703 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
3709 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
3711 /* Bit 1 : Pin 1 */
3712 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3715 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
3721 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
3730 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
3731 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3737 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
3738 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3744 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
3745 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3751 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
3752 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3758 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
3759 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3765 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
3766 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3772 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
3773 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3779 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
3780 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3786 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
3787 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3793 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
3794 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3800 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
3801 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3807 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
3808 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3814 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
3815 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3821 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
3822 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3828 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
3829 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3835 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
3836 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3842 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
3843 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3849 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
3850 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3856 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
3857 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3863 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
3864 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3870 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
3871 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3877 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
3878 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
3884 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
3885 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3891 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
3892 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3898 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
3899 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3905 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
3906 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3912 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
3913 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3919 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
3920 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3926 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
3927 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3933 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
3934 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3936 /* Bit 1 : Set as output pin 1 */
3937 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3940 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
3941 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3947 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
3948 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
3957 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
3958 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3964 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
3965 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3971 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
3972 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3978 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
3979 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3985 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
3986 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3992 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
3993 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
3999 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
4000 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4006 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
4007 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4013 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
4014 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4020 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
4021 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4027 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
4028 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4034 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
4035 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4041 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
4042 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4048 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
4049 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4055 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
4056 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4062 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
4063 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4069 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
4070 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4076 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
4077 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4083 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
4084 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4090 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
4091 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4097 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
4098 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4104 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
4105 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
4111 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
4112 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4118 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
4119 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4125 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
4126 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4132 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
4133 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4139 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
4140 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4146 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
4147 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4153 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
4154 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4160 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
4161 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4163 /* Bit 1 : Set as input pin 1 */
4164 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4167 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
4168 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4174 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
4175 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
4180 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to …
4184 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
4186 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to …
4190 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
4192 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to …
4196 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
4198 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to …
4202 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
4204 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to …
4208 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
4210 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to …
4214 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
4216 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to …
4220 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
4222 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to …
4226 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
4228 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to …
4232 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
4234 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to …
4238 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
4240 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to …
4244 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
4246 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to …
4250 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
4252 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to …
4256 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
4258 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to …
4262 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
4264 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to …
4268 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
4270 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to …
4274 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
4276 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to …
4280 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
4282 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to …
4286 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
4288 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to …
4292 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
4294 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to …
4298 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
4300 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to …
4304 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
4306 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to …
4310 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
4312 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to cle…
4316 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
4318 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to cle…
4322 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
4324 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to cle…
4328 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
4330 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to cle…
4334 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
4336 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to cle…
4340 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
4342 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to cle…
4346 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
4348 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to cle…
4352 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
4354 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
4358 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
4360 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to cle…
4361 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
4364 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
4366 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to cle…
4370 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
4379 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
4388 #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
4403 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
4404 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
4405 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
4406 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
4407 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or …
4408 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-…
4409 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-an…
4410 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-…
4416 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
4419 /* Bit 1 : Connect or disconnect input buffer */
4420 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
4423 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
4429 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
4441 #define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
4449 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
4458 #define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
4471 #define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
4484 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
4493 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
4502 #define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
4511 #define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
4524 #define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
4537 #define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
4550 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
4552 /* Bit 1 : Enable or disable interrupt for event STOPPED */
4553 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4556 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
4562 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4567 /* Bit 2 : Write '1' to enable interrupt for event END */
4571 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
4572 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
4574 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
4575 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4578 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4579 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
4581 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
4585 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4586 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
4591 /* Bit 2 : Write '1' to disable interrupt for event END */
4595 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
4596 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
4598 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
4599 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4602 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4603 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
4605 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
4609 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4610 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4619 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
4637 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
4638 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
4641 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
4647 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit eac…
4676 #define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
4685 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
4698 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
4728 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
4736 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
4745 #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */
4758 #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */
4771 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
4780 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
4789 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
4798 #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */
4811 #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */
4824 #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */
4837 #define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */
4843 #define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */
4849 #define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */
4854 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
4858 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4859 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
4861 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
4865 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4866 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
4868 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
4872 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4873 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
4878 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
4882 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4883 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
4885 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
4889 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4890 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
4892 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
4896 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4897 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
4906 #define POWER_RESETREAS_CTRLAP_Detected (1UL) /*!< Detected */
4912 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
4918 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
4924 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
4930 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
4932 /* Bit 1 : Reset from global watchdog detected */
4933 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
4936 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
4942 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
4951 #define POWER_POWERSTATUS_LTEMODEM_ON (1UL) /*!< LTE modem domain is powered on */
4970 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
4978 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
4986 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
4995 #define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5008 #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */
5021 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */
5034 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
5043 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
5052 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
5061 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
5070 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
5079 #define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
5092 #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
5105 #define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */
5118 #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */
5131 #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */
5144 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
5146 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
5150 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
5156 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
5158 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
5159 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
5162 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
5168 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
5177 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
5183 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
5185 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
5189 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
5195 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
5197 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
5201 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
5207 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
5209 /* Bit 1 : Enable or disable interrupt for event STOPPED */
5210 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5213 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
5218 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
5222 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5223 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
5225 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
5229 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5230 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
5232 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
5236 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5237 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
5239 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
5243 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5244 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
5246 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
5250 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5251 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
5253 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
5257 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5258 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
5260 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
5261 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5264 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5265 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
5270 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
5274 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5275 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
5277 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
5281 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5282 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
5284 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
5288 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5289 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
5291 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
5295 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5296 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
5298 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
5302 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5303 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
5305 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
5309 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5310 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
5312 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
5313 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5316 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5317 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
5326 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5335 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
5350 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */
5351 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
5354 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */
5366 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to inter…
5368 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
5371 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
5372 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word i…
5373 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4t…
5374 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th …
5402 … PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
5421 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
5437 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */
5442 /* Bits 4..1 : Power-fail comparator threshold setting */
5443 #define REGULATORS_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
5460 #define REGULATORS_POFCON_POF_Enabled (1UL) /*!< Enable */
5469 #define REGULATORS_DCDCEN_DCDCEN_Enabled (1UL) /*!< DC/DC mode is enabled */
5481 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5489 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5497 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
5505 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
5514 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5527 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5540 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
5553 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */
5566 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
5575 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
5584 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
5593 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */
5606 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */
5619 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
5628 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
5632 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5633 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
5635 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
5639 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5640 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
5642 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
5646 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5647 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
5649 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
5653 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5654 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
5656 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
5657 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5660 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5661 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
5663 /* Bit 0 : Write '1' to enable interrupt for event TICK */
5667 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5668 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
5673 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
5677 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5678 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5680 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
5684 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5685 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
5687 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
5691 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5692 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
5694 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
5698 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5699 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5701 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
5702 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5705 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5706 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5708 /* Bit 0 : Write '1' to disable interrupt for event TICK */
5712 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5713 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
5722 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
5728 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
5730 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
5734 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
5740 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
5742 /* Bit 1 : Enable or disable event routing for event OVRFLW */
5743 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5746 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
5752 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
5757 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
5761 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5762 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
5764 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
5768 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5769 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
5771 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
5775 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5776 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
5778 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
5782 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5783 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
5785 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
5786 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5789 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5790 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
5792 /* Bit 0 : Write '1' to enable event routing for event TICK */
5796 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5797 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
5802 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
5806 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5807 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5809 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
5813 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
5814 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
5816 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
5820 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
5821 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
5823 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
5827 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5828 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5830 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
5831 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5834 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5835 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5837 /* Bit 0 : Write '1' to disable event routing for event TICK */
5841 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5842 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
5852 /* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when …
5875 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5883 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
5891 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5899 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
5908 #define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5921 #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */
5934 #define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5947 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */
5960 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
5969 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
5978 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
5987 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
5996 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
6005 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
6014 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
6023 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
6032 #define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
6045 #define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
6058 #define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
6071 #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */
6084 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */
6097 #define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6110 #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */
6123 #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */
6136 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
6142 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
6148 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
6154 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
6160 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
6166 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
6172 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
6178 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
6184 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
6190 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
6196 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
6202 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
6208 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
6214 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
6220 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
6226 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
6232 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6238 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
6244 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
6250 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
6252 /* Bit 1 : Enable or disable interrupt for event END */
6253 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
6256 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
6262 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6267 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
6271 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6272 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
6274 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
6278 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6279 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
6281 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
6285 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6286 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
6288 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
6292 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6293 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
6295 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
6299 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6300 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
6302 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
6306 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6307 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
6309 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
6313 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6314 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
6316 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
6320 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6321 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
6323 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
6327 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6328 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
6330 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
6334 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6335 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
6337 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
6341 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6342 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
6344 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
6348 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6349 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
6351 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
6355 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6356 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
6358 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
6362 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6363 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
6365 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
6369 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6370 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
6372 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
6376 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6377 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
6379 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
6383 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6384 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6386 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
6390 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6391 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
6393 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
6397 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6398 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
6400 /* Bit 2 : Write '1' to enable interrupt for event DONE */
6404 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
6405 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
6407 /* Bit 1 : Write '1' to enable interrupt for event END */
6408 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
6411 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6412 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
6414 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
6418 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6419 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
6424 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
6428 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
6429 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
6431 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
6435 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
6436 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
6438 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
6442 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
6443 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
6445 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
6449 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
6450 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
6452 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
6456 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
6457 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
6459 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
6463 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
6464 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
6466 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
6470 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
6471 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
6473 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
6477 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
6478 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
6480 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
6484 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
6485 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
6487 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
6491 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
6492 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
6494 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
6498 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
6499 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
6501 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
6505 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
6506 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
6508 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
6512 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
6513 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
6515 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
6519 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
6520 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
6522 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
6526 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
6527 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
6529 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
6533 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
6534 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
6536 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
6540 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6541 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6543 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
6547 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
6548 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
6550 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
6554 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
6555 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
6557 /* Bit 2 : Write '1' to disable interrupt for event DONE */
6561 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
6562 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
6564 /* Bit 1 : Write '1' to disable interrupt for event END */
6565 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
6568 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6569 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
6571 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
6575 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6576 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6585 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
6594 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
6603 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
6620 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
6637 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
6643 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
6649 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
6659 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
6664 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
6665 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
6666 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
6667 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
6668 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
6669 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
6677 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
6681 /* Bits 1..0 : Positive channel resistor control */
6685 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
6707 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
6718 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
6734 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to cont…
6771 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6779 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6787 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
6795 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
6804 #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
6817 #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
6830 #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
6843 #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
6856 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
6865 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
6874 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
6883 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
6892 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
6901 #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
6914 #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
6927 #define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
6940 #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
6953 #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */
6966 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
6971 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
6975 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6976 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6978 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
6982 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
6983 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
6985 /* Bit 6 : Write '1' to enable interrupt for event END */
6989 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6990 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
6992 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
6996 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
6997 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
6999 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
7000 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7003 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7004 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
7009 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
7013 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7014 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
7016 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
7020 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7021 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
7023 /* Bit 6 : Write '1' to disable interrupt for event END */
7027 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7028 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
7030 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7034 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7035 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7037 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
7038 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7041 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7042 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
7060 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7073 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
7086 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
7101 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
7130 /* Bits 1..0 : List type */
7134 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7160 /* Bits 1..0 : List type */
7164 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
7173 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
7175 /* Bit 1 : Serial clock (SCK) phase */
7176 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
7179 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on…
7185 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
7204 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
7212 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
7221 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */
7234 #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */
7247 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
7256 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
7265 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
7274 #define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
7287 #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
7300 #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */
7313 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
7318 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
7322 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7323 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
7325 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
7329 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7330 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
7332 /* Bit 1 : Write '1' to enable interrupt for event END */
7333 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
7336 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7337 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
7342 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
7346 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
7347 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
7349 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
7353 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7354 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
7356 /* Bit 1 : Write '1' to disable interrupt for event END */
7357 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
7360 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7361 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
7366 /* Bits 1..0 : Semaphore status */
7370 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
7377 /* Bit 1 : RX buffer overflow detected, and prevented */
7378 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
7381 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
7382 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
7388 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
7389 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
7407 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7420 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
7433 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
7446 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
7501 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
7503 /* Bit 1 : Serial clock (SCK) phase */
7504 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
7507 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on…
7513 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
7540 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL) /*!< Event generated */
7549 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL) /*!< Event generated */
7558 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL) /*!< Event generated */
7567 #define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7580 #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7593 #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */
7606 #define SPU_INTEN_PERIPHACCERR_Enabled (1UL) /*!< Enable */
7608 /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */
7609 #define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
7612 #define SPU_INTEN_FLASHACCERR_Enabled (1UL) /*!< Enable */
7618 #define SPU_INTEN_RAMACCERR_Enabled (1UL) /*!< Enable */
7623 /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */
7627 #define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7628 #define SPU_INTENSET_PERIPHACCERR_Set (1UL) /*!< Enable */
7630 /* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */
7631 #define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
7634 #define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7635 #define SPU_INTENSET_FLASHACCERR_Set (1UL) /*!< Enable */
7637 /* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */
7641 #define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
7642 #define SPU_INTENSET_RAMACCERR_Set (1UL) /*!< Enable */
7647 /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */
7651 #define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */
7652 #define SPU_INTENCLR_PERIPHACCERR_Clear (1UL) /*!< Disable */
7654 /* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */
7655 #define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */
7658 #define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */
7659 #define SPU_INTENCLR_FLASHACCERR_Clear (1UL) /*!< Disable */
7661 /* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */
7665 #define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */
7666 #define SPU_INTENCLR_RAMACCERR_Clear (1UL) /*!< Disable */
7675 #define SPU_CAP_TZM_Enabled (1UL) /*!< ARM TrustZone support is available */
7684 #define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed unt…
7690 #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attr…
7692 /* Bits 1..0 : Define configuration capabilities  for TrustZone Cortex-M secure attribute */
7696 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL) /*!< The bus access from this external domain…
7706 #define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel15 has its secure attribute set */
7712 #define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel14 has its secure attribute set */
7718 #define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel13 has its secure attribute set */
7724 #define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel12 has its secure attribute set */
7730 #define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel11 has its secure attribute set */
7736 #define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel10 has its secure attribute set */
7742 #define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel9 has its secure attribute set */
7748 #define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel8 has its secure attribute set */
7754 #define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel7 has its secure attribute set */
7760 #define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel6 has its secure attribute set */
7766 #define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel5 has its secure attribute set */
7772 #define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel4 has its secure attribute set */
7778 #define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel3 has its secure attribute set */
7784 #define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel2 has its secure attribute set */
7786 /* Bit 1 : Select secure attribute. */
7787 #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */
7790 #define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel1 has its secure attribute set */
7796 #define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel0 has its secure attribute set */
7805 #define SPU_DPPI_LOCK_LOCK_Locked (1UL) /*!< DPPI[n].PERM register can't be changed until next rese…
7814 #define SPU_GPIOPORT_PERM_PIN31_Secure (1UL) /*!< Pin 31 has its secure attribute set */
7820 #define SPU_GPIOPORT_PERM_PIN30_Secure (1UL) /*!< Pin 30 has its secure attribute set */
7826 #define SPU_GPIOPORT_PERM_PIN29_Secure (1UL) /*!< Pin 29 has its secure attribute set */
7832 #define SPU_GPIOPORT_PERM_PIN28_Secure (1UL) /*!< Pin 28 has its secure attribute set */
7838 #define SPU_GPIOPORT_PERM_PIN27_Secure (1UL) /*!< Pin 27 has its secure attribute set */
7844 #define SPU_GPIOPORT_PERM_PIN26_Secure (1UL) /*!< Pin 26 has its secure attribute set */
7850 #define SPU_GPIOPORT_PERM_PIN25_Secure (1UL) /*!< Pin 25 has its secure attribute set */
7856 #define SPU_GPIOPORT_PERM_PIN24_Secure (1UL) /*!< Pin 24 has its secure attribute set */
7862 #define SPU_GPIOPORT_PERM_PIN23_Secure (1UL) /*!< Pin 23 has its secure attribute set */
7868 #define SPU_GPIOPORT_PERM_PIN22_Secure (1UL) /*!< Pin 22 has its secure attribute set */
7874 #define SPU_GPIOPORT_PERM_PIN21_Secure (1UL) /*!< Pin 21 has its secure attribute set */
7880 #define SPU_GPIOPORT_PERM_PIN20_Secure (1UL) /*!< Pin 20 has its secure attribute set */
7886 #define SPU_GPIOPORT_PERM_PIN19_Secure (1UL) /*!< Pin 19 has its secure attribute set */
7892 #define SPU_GPIOPORT_PERM_PIN18_Secure (1UL) /*!< Pin 18 has its secure attribute set */
7898 #define SPU_GPIOPORT_PERM_PIN17_Secure (1UL) /*!< Pin 17 has its secure attribute set */
7904 #define SPU_GPIOPORT_PERM_PIN16_Secure (1UL) /*!< Pin 16 has its secure attribute set */
7910 #define SPU_GPIOPORT_PERM_PIN15_Secure (1UL) /*!< Pin 15 has its secure attribute set */
7916 #define SPU_GPIOPORT_PERM_PIN14_Secure (1UL) /*!< Pin 14 has its secure attribute set */
7922 #define SPU_GPIOPORT_PERM_PIN13_Secure (1UL) /*!< Pin 13 has its secure attribute set */
7928 #define SPU_GPIOPORT_PERM_PIN12_Secure (1UL) /*!< Pin 12 has its secure attribute set */
7934 #define SPU_GPIOPORT_PERM_PIN11_Secure (1UL) /*!< Pin 11 has its secure attribute set */
7940 #define SPU_GPIOPORT_PERM_PIN10_Secure (1UL) /*!< Pin 10 has its secure attribute set */
7946 #define SPU_GPIOPORT_PERM_PIN9_Secure (1UL) /*!< Pin 9 has its secure attribute set */
7952 #define SPU_GPIOPORT_PERM_PIN8_Secure (1UL) /*!< Pin 8 has its secure attribute set */
7958 #define SPU_GPIOPORT_PERM_PIN7_Secure (1UL) /*!< Pin 7 has its secure attribute set */
7964 #define SPU_GPIOPORT_PERM_PIN6_Secure (1UL) /*!< Pin 6 has its secure attribute set */
7970 #define SPU_GPIOPORT_PERM_PIN5_Secure (1UL) /*!< Pin 5 has its secure attribute set */
7976 #define SPU_GPIOPORT_PERM_PIN4_Secure (1UL) /*!< Pin 4 has its secure attribute set */
7982 #define SPU_GPIOPORT_PERM_PIN3_Secure (1UL) /*!< Pin 3 has its secure attribute set */
7988 #define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */
7990 /* Bit 1 : Select secure attribute attribute for PIN 1. */
7991 #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
7993 #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */
7994 #define SPU_GPIOPORT_PERM_PIN1_Secure (1UL) /*!< Pin 1 has its secure attribute set */
8000 #define SPU_GPIOPORT_PERM_PIN0_Secure (1UL) /*!< Pin 0 has its secure attribute set */
8009 #define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL) /*!< GPIOPORT[n].PERM register can't be changed until n…
8018 #define SPU_FLASHNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed un…
8031 #define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed unti…
8037 #define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a …
8053 #define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed unti…
8066 #define SPU_RAMNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until …
8072 #define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32…
8088 #define SPU_FLASHREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed u…
8094 #define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL) /*!< Flash region n security attribute is secure …
8100 #define SPU_FLASHREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from flash region n */
8102 /* Bit 1 : Configure write permission for flash region n */
8103 #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
8106 #define SPU_FLASHREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to region n */
8112 #define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from flash region …
8121 #define SPU_RAMREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed unt…
8127 #define SPU_RAMREGION_PERM_SECATTR_Secure (1UL) /*!< RAM region n security attribute is secure */
8133 #define SPU_RAMREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from RAM region n */
8135 /* Bit 1 : Configure write permission for RAM region n */
8136 #define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
8139 #define SPU_RAMREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to RAM region n */
8145 #define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from RAM region n */
8154 #define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL) /*!< Peripheral is present */
8160 #define SPU_PERIPHID_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed unti…
8166 #define SPU_PERIPHID_PERM_DMASEC_Secure (1UL) /*!< DMA transfers initiated by this peripheral have …
8172 #define SPU_PERIPHID_PERM_SECATTR_Secure (1UL) /*!< Peripheral is mapped in secure peripheral addre…
8178 #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers a…
8181 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */
8185 #define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL) /*!< This peripheral is always accessible as a…
8200 #define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */
8209 #define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
8222 #define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL) /*!< Disconnect */
8229 /* Description: Pin number configuration for TRACEDATA[1] */
8235 #define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL) /*!< Disconnect */
8248 #define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL) /*!< Disconnect */
8261 #define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL) /*!< Disconnect */
8270 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided…
8274 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MH…
8288 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8296 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8304 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
8312 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
8320 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
8328 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
8337 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
8350 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8363 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */
8376 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
8389 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */
8402 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
8415 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
8424 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
8437 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
8443 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
8449 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
8455 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
8457 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
8461 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
8467 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
8473 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8479 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8485 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8491 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8493 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
8494 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
8497 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8503 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8508 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
8512 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8513 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
8515 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
8519 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8520 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
8522 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
8526 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8527 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
8529 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
8533 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8534 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
8536 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
8540 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8541 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
8543 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
8547 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8548 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
8553 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
8557 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8558 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
8560 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
8564 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8565 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
8567 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
8571 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8572 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
8574 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
8578 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8579 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
8581 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
8585 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8586 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
8588 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
8592 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8593 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
8598 /* Bits 1..0 : Timer mode */
8602 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
8608 /* Bits 1..0 : Timer bit width */
8612 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
8640 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
8648 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
8656 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8664 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
8672 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
8681 #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
8694 #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
8707 #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
8720 #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
8733 #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
8746 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8755 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
8764 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
8773 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
8782 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
8791 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
8800 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
8809 #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
8822 #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
8835 #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */
8848 #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
8861 #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
8874 #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */
8887 #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */
8900 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
8906 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8912 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
8918 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
8924 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
8930 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
8939 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
8945 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
8951 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
8957 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
8963 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
8969 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
8971 /* Bit 1 : Enable or disable interrupt for event STOPPED */
8972 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8975 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8980 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
8984 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8985 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
8987 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
8991 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
8992 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
8994 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
8998 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8999 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9001 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9005 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9006 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9008 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
9012 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9013 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
9015 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9019 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9020 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
9022 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9023 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9026 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9027 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9032 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
9036 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
9037 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
9039 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
9043 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
9044 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
9046 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9050 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9051 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9053 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9057 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9058 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9060 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
9064 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9065 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
9067 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9071 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9072 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9074 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9075 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9078 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9079 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9084 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
9088 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
9090 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
9091 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
9094 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
9100 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
9118 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9131 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9171 /* Bits 1..0 : List type */
9175 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9201 /* Bits 1..0 : List type */
9205 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9224 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9232 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
9240 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
9248 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
9256 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
9265 #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
9278 #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */
9291 #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */
9304 #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */
9317 #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */
9330 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9339 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9348 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
9357 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
9366 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
9375 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
9384 #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */
9397 #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
9410 #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
9423 #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
9436 #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */
9449 #define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */
9462 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9468 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9477 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
9483 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
9489 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9495 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9501 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9503 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9504 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9507 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9512 /* Bit 26 : Write '1' to enable interrupt for event READ */
9516 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
9517 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
9519 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
9523 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
9524 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
9526 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
9530 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9531 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9533 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9537 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9538 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9540 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9544 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9545 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
9547 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9548 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9551 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9552 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9557 /* Bit 26 : Write '1' to disable interrupt for event READ */
9561 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
9562 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
9564 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
9568 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
9569 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
9571 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9575 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9576 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9578 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9582 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9583 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9585 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9589 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9590 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9592 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9593 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9596 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9597 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9606 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
9612 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
9618 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
9643 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9656 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9714 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
9715 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
9718 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
9724 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
9743 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
9751 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
9759 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
9767 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
9775 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
9784 #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */
9797 #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */
9810 #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */
9823 #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */
9836 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */
9849 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
9858 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
9867 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
9876 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
9885 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
9894 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
9903 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9912 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
9921 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
9930 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
9939 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
9948 #define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */
9961 #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */
9974 #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
9987 #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */
10000 #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */
10013 #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */
10026 #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
10039 #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */
10052 #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10065 #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
10078 #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
10091 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
10097 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
10106 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
10112 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
10118 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
10124 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
10130 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
10136 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
10142 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
10148 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
10154 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
10156 /* Bit 1 : Enable or disable interrupt for event NCTS */
10157 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10160 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
10166 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
10171 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
10175 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10176 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
10178 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
10182 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10183 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
10185 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
10189 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10190 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
10192 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
10196 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
10197 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
10199 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
10203 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10204 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
10206 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
10210 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10211 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10213 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
10217 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10218 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
10220 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
10224 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10225 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10227 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
10231 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10232 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
10234 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
10235 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10238 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
10239 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
10241 /* Bit 0 : Write '1' to enable interrupt for event CTS */
10245 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
10246 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
10251 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
10255 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10256 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
10258 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
10262 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10263 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
10265 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
10269 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10270 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
10272 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
10276 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
10277 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
10279 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
10283 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10284 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
10286 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
10290 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10291 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10293 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
10297 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10298 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
10300 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
10304 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10305 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10307 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
10311 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10312 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
10314 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
10315 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10318 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
10319 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
10321 /* Bit 0 : Write '1' to disable interrupt for event CTS */
10325 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
10326 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
10335 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
10341 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
10343 /* Bit 1 : Parity error */
10344 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10347 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
10353 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
10371 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10384 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10397 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10410 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10439 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
10490 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
10492 /* Bits 3..1 : Parity */
10493 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10502 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
10532 #define UICR_HFXOSRC_HFXOSRC_XTAL (1UL) /*!< 32 MHz crystal oscillator */
10580 /* Description: Description cluster: Define permissions for the key slot with ID=n+1. Bits 0-15 and…
10586 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL) /*!< Key value registers are readable (if enabl…
10592 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL) /*!< Enable pushing of key value registers over…
10594 /* Bit 1 : Read permission for key slot */
10595 #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */
10598 #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */
10604 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */
10607 …n: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot ID=n+1 */
10609 /* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot ID=n+1 */
10624 #define VMC_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
10630 #define VMC_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
10636 #define VMC_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
10642 #define VMC_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
10648 #define VMC_RAM_POWER_S3POWER_On (1UL) /*!< On */
10654 #define VMC_RAM_POWER_S2POWER_On (1UL) /*!< On */
10656 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
10657 #define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
10660 #define VMC_RAM_POWER_S1POWER_On (1UL) /*!< On */
10666 #define VMC_RAM_POWER_S0POWER_On (1UL) /*!< On */
10674 #define VMC_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
10679 #define VMC_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
10684 #define VMC_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
10689 #define VMC_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
10694 #define VMC_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
10699 #define VMC_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
10701 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
10702 #define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
10704 #define VMC_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
10709 #define VMC_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
10717 #define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
10722 #define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
10727 #define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
10732 #define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
10737 #define VMC_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
10742 #define VMC_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
10744 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */
10745 #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
10747 #define VMC_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
10752 #define VMC_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
10764 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
10773 #define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
10786 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
10795 #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */
10804 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
10808 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10809 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
10814 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
10818 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10819 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
10828 #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */
10837 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not y…
10843 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not y…
10849 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not y…
10855 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not y…
10861 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not y…
10867 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
10869 /* Bit 1 : Request status for RR[1] register */
10870 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
10872 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are alre…
10873 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not y…
10879 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not y…
10895 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
10901 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
10907 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
10913 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
10919 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
10925 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
10927 /* Bit 1 : Enable or disable RR[1] register */
10928 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
10930 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
10931 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
10937 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
10946 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the deb…
10952 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */