Lines Matching full:enabled

48 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
55 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
62 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
72 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
79 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
86 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
339 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
345 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
351 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
357 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
363 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
369 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
375 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
381 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
387 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
393 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
399 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
405 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
411 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
417 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
423 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
429 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
435 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
441 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
447 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
453 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
459 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
465 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
471 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
477 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
483 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
489 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
495 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
501 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
507 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
513 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
519 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
525 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
543 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
549 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
555 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
561 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
567 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
573 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
579 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
585 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
591 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
597 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
603 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
609 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
615 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
621 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
627 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
633 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
639 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
645 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
651 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
657 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
663 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
669 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
675 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
681 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
687 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
693 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
699 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
705 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
711 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
717 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
723 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
729 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
738 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
744 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
750 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
756 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
762 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
768 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
774 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
780 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
786 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
792 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
798 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
804 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
810 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
816 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
822 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
828 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
834 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
840 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
846 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
852 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
858 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
864 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
870 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
876 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
882 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
888 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
894 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
900 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
906 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
912 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
918 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
924 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
946 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
953 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
960 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
970 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
977 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
984 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
1065 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
1072 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
1079 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1086 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1096 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
1103 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
1110 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1117 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1297 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1304 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1311 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1318 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1328 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1335 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1342 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1349 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1446 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1455 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
1456 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
1457 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
1470 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1477 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1487 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1494 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1614 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1621 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1628 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1635 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1642 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1649 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1656 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1663 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1670 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1677 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1684 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1691 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1698 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1705 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1712 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1719 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1729 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1736 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1743 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1750 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1757 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1764 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1771 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1778 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1785 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1792 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1799 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1806 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1813 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1820 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1827 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1834 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
2155 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
2162 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
2169 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
2176 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
2183 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
2190 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
2197 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
2204 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
2211 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
2221 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2228 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
2235 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
2242 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
2249 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2256 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2263 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2270 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2277 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2340 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2347 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2354 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2364 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2371 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2378 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2406 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
2415 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2635 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2642 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2649 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2656 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2666 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2673 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2680 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2687 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2860 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2867 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2874 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2881 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2888 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2895 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2902 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2909 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2916 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2923 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2930 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2937 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2947 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2954 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2961 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2968 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2975 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2982 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2989 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2996 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3003 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3010 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3017 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3024 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3109 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3116 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3123 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3130 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3137 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3144 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3151 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3158 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3165 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3172 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3179 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3186 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3196 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3203 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3210 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3217 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3224 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3231 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3238 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3245 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3252 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3259 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3266 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3273 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3277 …errupt in region 0, write access detected while corresponding subregion was enabled for watching */
3472 …terrupt in region 0, read access detected while corresponding subregion was enabled for watching */
3748 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3755 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3762 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3769 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3776 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3783 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3790 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3797 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3804 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3811 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3818 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3825 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3835 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3842 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3849 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3856 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3863 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3870 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3877 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3884 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3891 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3898 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3905 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3912 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4257 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4264 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4271 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4278 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4285 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4292 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4299 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4306 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4313 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4320 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4327 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4334 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4341 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4348 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4355 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4365 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4372 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4379 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4386 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4393 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4400 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4407 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4414 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4421 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4428 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4435 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4442 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4449 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4456 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4463 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4759 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
4760 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
4779 …volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN bef…
4795 …User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN bef…
6604 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6611 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6618 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6628 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6635 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6642 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6750 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6757 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6764 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6774 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6781 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6788 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7258 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
7265 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
7272 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
7279 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
7286 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
7293 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
7300 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
7307 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
7314 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
7321 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
7328 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
7335 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
7342 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
7349 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
7356 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
7363 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
7370 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
7377 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
7384 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
7391 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
7398 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
7405 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
7412 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
7419 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
7426 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
7433 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
7440 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
7447 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
7454 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
7461 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
7468 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
7475 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
7485 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
7492 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
7499 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
7506 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
7513 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
7520 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
7527 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
7534 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
7541 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
7548 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
7555 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
7562 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
7569 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
7576 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
7583 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
7590 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
7597 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
7604 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
7611 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
7618 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
7625 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
7632 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
7639 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
7646 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
7653 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
7660 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
7667 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
7674 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
7681 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
7688 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
7695 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
7702 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
8010 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8017 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8024 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8031 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8038 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8045 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8052 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8062 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8069 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8076 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8083 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8090 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8097 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8104 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8271 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8278 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8285 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8292 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8299 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8309 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8316 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8323 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8330 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8337 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8459 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
8544 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8551 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8558 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8565 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8572 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8579 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8586 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8593 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8600 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8607 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8614 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
8624 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8631 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8638 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8645 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8652 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8659 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8666 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8673 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8680 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8687 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8694 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
8953 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
8954 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
8955 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled …
9068 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
9074 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
9080 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
9086 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
9092 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
9098 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
9104 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
9110 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
9157 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9167 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9177 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
9197 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9204 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9211 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9218 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9225 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9232 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9242 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9249 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9256 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9263 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9270 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9277 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9326 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9333 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9340 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9347 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9354 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9361 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9371 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9378 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9385 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9392 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9399 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9406 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9576 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9583 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9590 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9597 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9604 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9611 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9618 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9625 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9632 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9639 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9646 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9653 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9660 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9667 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9674 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9681 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9688 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9695 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9702 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9709 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
9716 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
9723 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
9733 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9740 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9747 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9754 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9761 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9768 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9775 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9782 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9789 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9796 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9803 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9810 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9817 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9824 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9831 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9838 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9845 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9852 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9859 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9866 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
9873 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
9880 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
9942 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
10077 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10087 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10192 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
10199 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10206 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10213 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10220 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10230 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
10237 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10244 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10251 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10258 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10431 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10438 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10445 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10455 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10462 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10469 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10649 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10659 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10874 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10881 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10888 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10895 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10902 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10909 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10919 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10926 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10933 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10940 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10947 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10954 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11018 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11025 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
11032 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11039 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11046 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11053 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11063 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11070 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
11077 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11084 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11091 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11098 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11270 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11277 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11284 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11291 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11298 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11305 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11312 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11322 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11329 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11336 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11343 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11350 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11357 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11364 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11565 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
11572 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
11579 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11586 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11593 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11600 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11610 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
11617 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
11624 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11631 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11638 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11645 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11767 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
11773 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
11808 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
11815 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11822 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11829 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11836 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
11843 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
11853 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
11860 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11867 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11874 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11881 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
11888 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
12011 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
12108 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12115 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12122 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12129 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
12136 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
12143 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12150 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12157 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12164 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12171 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
12178 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
12188 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12195 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12202 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12209 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
12216 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
12223 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12230 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12237 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12244 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12251 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
12258 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
12429 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
12498 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12508 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12526 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are alre…
12527 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not y…
12532 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are alre…
12533 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not y…
12538 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are alre…
12539 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not y…
12544 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are alre…
12545 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not y…
12550 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are alre…
12551 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not y…
12556 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are alre…
12557 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
12562 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are alre…
12563 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not y…
12568 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are alre…
12569 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not y…