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8 1. Redistributions of source code must retain the above copyright notice, this
44 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
48 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
49 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
51 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
52 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
55 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
56 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
58 /* Bit 0 : Write '1' to Enable interrupt for END event */
62 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
63 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
68 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
72 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
73 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
75 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
76 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
79 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
80 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
82 /* Bit 0 : Write '1' to Disable interrupt for END event */
86 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
87 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
99 /* Bits 1..0 : Enable or disable AAR */
144 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
150 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
156 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
162 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
168 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
174 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
180 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
186 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
192 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
198 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
204 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
210 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
216 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
222 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
228 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
234 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
240 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
246 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
252 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
258 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
264 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
270 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
276 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
282 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
288 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
294 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
300 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
306 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
312 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
318 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
320 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
321 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
324 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
330 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
333 /* Description: Block protect configuration register 1 */
339 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
345 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
351 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
357 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
363 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
369 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
375 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
381 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
387 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
393 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
399 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
405 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
411 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
417 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
423 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
429 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
435 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
441 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
447 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
453 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
459 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
465 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
471 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
477 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
483 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
489 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
495 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
501 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
507 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
513 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
515 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
516 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
519 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
525 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
534 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
543 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
549 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
555 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
561 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
567 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
573 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
579 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
585 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
591 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
597 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
603 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
609 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
615 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
621 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
627 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
633 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
639 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
645 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
651 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
657 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
663 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
669 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
675 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
681 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
687 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
693 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
699 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
705 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
711 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
717 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
719 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
720 #define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
723 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
729 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
738 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
744 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
750 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
756 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
762 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
768 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
774 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
780 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
786 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
792 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
798 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
804 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
810 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
816 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
822 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
828 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
834 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
840 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
846 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
852 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
858 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
864 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
870 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
876 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
882 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
888 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
894 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
900 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
906 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
912 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
914 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
915 #define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
918 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
924 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
937 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
942 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
946 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
947 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
949 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
950 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
953 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
954 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
956 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
960 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
961 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
966 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
970 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
971 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
973 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
974 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
977 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
978 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
980 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
984 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
985 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
994 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
999 /* Bits 1..0 : Enable or disable CCM */
1012 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-…
1017 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
1018 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
1024 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
1029 … the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure o…
1061 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */
1065 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
1066 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
1068 /* Bit 3 : Write '1' to Enable interrupt for DONE event */
1072 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
1073 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
1075 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
1076 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1079 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1080 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
1082 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
1086 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1087 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
1092 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */
1096 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
1097 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
1099 /* Bit 3 : Write '1' to Disable interrupt for DONE event */
1103 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
1104 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
1106 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
1107 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1110 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1111 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
1113 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
1117 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1118 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
1127 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1136 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
1142 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
1151 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1160 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
1162 /* Bits 1..0 : Source of LFCLK */
1166 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1172 /* Bits 1..0 : Clock source */
1176 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1186 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (S…
1192 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
1194 /* Bits 1..0 : Clock source */
1198 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1215 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed o…
1218 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided…
1222 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz…
1237 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
1243 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
1249 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
1251 /* Bit 1 : Shortcut between READY event and STOP task */
1252 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
1255 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
1261 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
1270 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
1276 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
1278 /* Bit 1 : Enable or disable interrupt for DOWN event */
1279 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1282 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
1288 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
1293 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
1297 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1298 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
1300 /* Bit 2 : Write '1' to Enable interrupt for UP event */
1304 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1305 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
1307 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
1308 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1311 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1312 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
1314 /* Bit 0 : Write '1' to Enable interrupt for READY event */
1318 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1319 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
1324 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
1328 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1329 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1331 /* Bit 2 : Write '1' to Disable interrupt for UP event */
1335 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1336 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1338 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
1339 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1342 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1343 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1345 /* Bit 0 : Write '1' to Disable interrupt for READY event */
1349 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1350 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1359 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
1364 /* Bits 1..0 : Enable or disable COMP */
1377 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
1392 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 …
1404 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference …
1415 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
1419 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1430 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1432 /* Bits 1..0 : Speed and power modes */
1436 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1446 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1451 /* Bits 1..0 : Comparator hysteresis */
1455 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
1466 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
1467 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1470 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1471 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1473 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
1477 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1478 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1483 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
1484 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1487 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1488 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1490 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
1494 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1495 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1500 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1515 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1521 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1527 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1533 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1539 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1545 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1551 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1557 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1563 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1569 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1575 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1581 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1587 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1593 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1595 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1596 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1599 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1605 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1610 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
1614 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1615 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1617 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
1621 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1622 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1624 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
1628 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1629 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1631 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
1635 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1636 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1638 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
1642 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1643 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1645 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
1649 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1650 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1652 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
1656 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1657 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1659 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
1663 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1664 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1666 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
1670 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1671 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1673 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
1677 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1678 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1680 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
1684 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1685 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1687 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
1691 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1692 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1694 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
1698 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1699 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1701 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
1705 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1706 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1708 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
1709 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1712 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1713 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1715 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
1719 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1720 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1725 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
1729 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1730 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1732 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
1736 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1737 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1739 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
1743 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1744 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1746 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
1750 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1751 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1753 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
1757 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1758 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1760 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
1764 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1765 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1767 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
1771 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1772 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1774 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
1778 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1779 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1781 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
1785 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1786 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1788 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
1792 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1793 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1795 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
1799 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1800 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1802 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
1806 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1807 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1809 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
1813 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1814 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1816 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
1820 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1821 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1823 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
1824 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1827 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1828 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1830 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
1834 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1835 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1883 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
2079 /* Bits 15..8 : Unique identifier byte 1 */
2151 /* Bit 31 : Write '1' to Enable interrupt for PORT event */
2155 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
2156 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
2158 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
2162 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
2163 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
2165 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
2169 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
2170 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
2172 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
2176 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
2177 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
2179 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
2183 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
2184 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
2186 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
2190 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
2191 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
2193 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
2197 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
2198 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
2200 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
2201 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
2204 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
2205 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
2207 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
2211 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
2212 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
2217 /* Bit 31 : Write '1' to Disable interrupt for PORT event */
2221 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2222 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
2224 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
2228 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
2229 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
2231 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
2235 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
2236 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
2238 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
2242 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
2243 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
2245 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
2249 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2250 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
2252 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
2256 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2257 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
2259 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
2263 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2264 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
2266 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
2267 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
2270 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2271 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
2273 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
2277 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2278 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
2287 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggerin…
2293 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: G…
2301 /* Bits 1..0 : Mode */
2305 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
2319 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
2325 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
2327 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
2328 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2331 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
2336 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
2340 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2341 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
2343 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
2347 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2348 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
2350 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
2351 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2354 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2355 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
2360 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
2364 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2365 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
2367 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
2371 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2372 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
2374 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
2375 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2378 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2379 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
2388 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2397 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master…
2406 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
2415 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2424 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on …
2458 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
2470 /* Bits 1..0 : Sample width. */
2474 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
2484 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2493 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2498 /* Bits 1..0 : Enable channels. */
2502 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
2533 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2546 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2559 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2572 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2585 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
2602 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
2608 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
2614 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
2616 /* Bit 1 : Shortcut between READY event and STOP task */
2617 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
2620 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
2626 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
2631 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
2635 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2636 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
2638 /* Bit 2 : Write '1' to Enable interrupt for UP event */
2642 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2643 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
2645 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
2646 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2649 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2650 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
2652 /* Bit 0 : Write '1' to Enable interrupt for READY event */
2656 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2657 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
2662 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
2666 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2667 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
2669 /* Bit 2 : Write '1' to Disable interrupt for UP event */
2673 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2674 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
2676 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
2677 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2680 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2681 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
2683 /* Bit 0 : Write '1' to Disable interrupt for READY event */
2687 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2688 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
2697 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ …
2702 /* Bits 1..0 : Enable or disable LPCOMP */
2706 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2715 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
2729 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
2730 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
2737 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
2753 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog referenc…
2758 /* Bits 1..0 : Analog detect configuration */
2762 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
2772 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
2781 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
2785 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2787 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
2791 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2797 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2803 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2809 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
2815 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
2821 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
2827 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
2829 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
2833 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
2835 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2839 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
2841 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
2842 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2845 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
2851 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
2856 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
2860 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2861 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
2863 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
2867 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2868 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
2870 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
2874 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2875 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
2877 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
2881 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2882 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
2884 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
2888 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2889 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
2891 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
2895 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2896 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
2898 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
2902 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2903 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
2905 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
2909 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2910 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
2912 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
2916 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2917 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
2919 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
2923 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2924 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
2926 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
2927 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2930 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2931 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
2933 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
2937 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2938 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
2943 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
2947 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2948 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
2950 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
2954 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2955 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
2957 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
2961 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2962 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
2964 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
2968 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2969 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
2971 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
2975 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2976 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
2978 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
2982 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2983 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
2985 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
2989 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2990 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
2992 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
2996 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2997 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
2999 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
3003 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3004 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3006 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
3010 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3011 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3013 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
3014 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3017 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3018 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3020 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
3024 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3025 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3030 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
3034 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
3036 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
3040 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
3046 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
3052 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
3058 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
3064 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
3070 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
3076 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
3078 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
3082 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
3084 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
3088 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
3090 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
3091 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3094 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
3100 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
3105 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
3109 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3110 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
3112 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
3116 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3117 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
3119 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
3123 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3124 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
3126 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
3130 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3131 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
3133 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
3137 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3138 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
3140 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
3144 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3145 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
3147 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
3151 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3152 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
3154 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
3158 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3159 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
3161 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
3165 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3166 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
3168 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
3172 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3173 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
3175 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
3176 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3179 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3180 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
3182 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
3186 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3187 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
3192 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
3196 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3197 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3199 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
3203 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3204 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3206 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
3210 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3211 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3213 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
3217 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3218 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3220 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
3224 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3225 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3227 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
3231 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3232 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3234 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
3238 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3239 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3241 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
3245 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3246 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3248 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
3252 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3253 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3255 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
3259 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3260 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3262 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
3263 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3266 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3267 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3269 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
3273 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3274 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3279 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3283 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion …
3285 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3289 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion …
3291 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3295 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion …
3297 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3301 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion …
3303 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3307 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion …
3309 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3313 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion …
3315 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3319 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion …
3321 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3325 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion …
3327 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3331 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion …
3333 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3337 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion …
3339 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3343 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion …
3345 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3349 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion …
3351 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3355 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion …
3357 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3361 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion …
3363 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3367 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion …
3369 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3373 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion …
3375 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3379 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion …
3381 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3385 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion …
3387 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3391 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion …
3393 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3397 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion …
3399 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3403 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion …
3405 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3409 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion …
3411 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3415 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
3417 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3421 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
3423 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3427 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
3429 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3433 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
3435 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3439 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
3441 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3445 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
3447 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3451 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
3453 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3457 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
3459 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3460 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3463 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
3465 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3469 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
3474 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3478 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
3480 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3484 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
3486 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3490 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
3492 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3496 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
3498 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3502 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
3504 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3508 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
3510 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3514 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
3516 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3520 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
3522 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3526 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
3528 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3532 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
3534 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3538 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
3540 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3544 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
3546 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3550 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
3552 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3556 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
3558 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3562 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
3564 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3568 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
3570 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3574 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
3576 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3580 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
3582 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3586 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
3588 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3592 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
3594 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3598 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
3600 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3604 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
3606 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3610 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
3612 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3616 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
3618 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3622 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
3624 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3628 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
3630 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3634 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
3636 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3640 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
3642 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3646 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
3648 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3652 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
3654 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3655 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3658 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
3660 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3664 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
3669 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3673 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3675 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3679 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3685 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3691 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3697 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3703 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3709 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3715 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3717 /* Bit 3 : Enable/disable read access watch in region[1] */
3721 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3723 /* Bit 2 : Enable/disable write access watch in region[1] */
3727 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3729 /* Bit 1 : Enable/disable read access watch in region[0] */
3730 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3733 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3739 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3744 /* Bit 27 : Enable read access watch in PREGION[1] */
3748 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3749 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3751 /* Bit 26 : Enable write access watch in PREGION[1] */
3755 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3756 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3762 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3763 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3769 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3770 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3776 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3777 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3783 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3784 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3790 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3791 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3797 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3798 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3800 /* Bit 3 : Enable read access watch in region[1] */
3804 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3805 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3807 /* Bit 2 : Enable write access watch in region[1] */
3811 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3812 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3814 /* Bit 1 : Enable read access watch in region[0] */
3815 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3818 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3819 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3825 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3826 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
3831 /* Bit 27 : Disable read access watch in PREGION[1] */
3835 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3836 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3838 /* Bit 26 : Disable write access watch in PREGION[1] */
3842 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3843 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3849 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3850 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3856 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3857 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3863 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3864 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3870 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3871 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3877 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3878 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3884 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3885 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3887 /* Bit 3 : Disable read access watch in region[1] */
3891 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3892 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3894 /* Bit 2 : Disable write access watch in region[1] */
3898 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3899 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3901 /* Bit 1 : Disable read access watch in region[0] */
3902 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3905 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3906 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
3912 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3913 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
3950 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
3956 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
3962 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
3968 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
3974 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
3980 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
3986 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
3992 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
3998 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
4004 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
4010 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
4016 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
4022 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
4028 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
4034 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
4040 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
4046 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
4052 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
4058 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
4064 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
4070 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
4076 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
4082 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
4088 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
4094 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
4100 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
4106 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
4112 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
4118 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
4124 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
4126 /* Bit 1 : Include or exclude subregion 1 in region */
4127 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
4130 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
4136 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
4145 /* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
4146 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
4149 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
4155 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
4164 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4170 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
4176 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
4182 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
4188 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
4194 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
4200 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
4206 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
4212 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
4218 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
4224 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
4230 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
4236 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
4238 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
4239 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4242 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
4248 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
4253 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */
4257 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4258 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
4260 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
4264 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4265 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
4267 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
4271 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4272 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
4274 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
4278 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4279 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
4281 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
4285 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4286 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
4288 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
4292 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4293 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
4295 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
4299 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4300 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
4302 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */
4306 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4307 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
4309 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
4313 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4314 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
4316 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
4320 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4321 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
4323 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
4327 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4328 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
4330 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
4334 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4335 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
4337 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
4341 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4342 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
4344 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
4345 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4348 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4349 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
4351 /* Bit 0 : Write '1' to Enable interrupt for READY event */
4355 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4356 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
4361 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */
4365 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4366 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4368 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
4372 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4373 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
4375 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
4379 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4380 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
4382 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
4386 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4387 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
4389 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
4393 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4394 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
4396 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
4400 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4401 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
4403 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
4407 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4408 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
4410 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */
4414 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4415 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
4417 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
4421 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4422 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
4424 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
4428 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4429 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
4431 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
4435 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4436 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
4438 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
4442 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4443 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
4445 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
4449 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4450 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
4452 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
4453 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4456 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4457 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
4459 /* Bit 0 : Write '1' to Disable interrupt for READY event */
4463 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4464 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
4488 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
4494 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
4500 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
4512 /* Bit 1 : Indicates if the low level has locked to the field */
4513 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
4516 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
4522 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
4541 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
4545 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELA…
4570 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on al…
4576 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
4578 /* Bit 1 : Discarding unused bits in start or at end of a Frame */
4579 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
4582 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start …
4588 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
4608 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is c…
4614 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
4620 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
4697 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
4704 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Foru…
4708 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
4733 #define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
4735 /* Bits 1..0 : Reserved for future use. Shall be 0. */
4750 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
4755 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and wr…
4759 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
4783 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
4799 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
4808 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
4814 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
4832 /* Description: GPIO Port 1 */
4841 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
4847 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
4853 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
4859 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
4865 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
4871 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
4877 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
4883 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
4889 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
4895 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
4901 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
4907 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
4913 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
4919 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
4925 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
4931 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
4937 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
4943 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
4949 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
4955 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
4961 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
4967 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
4973 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
4979 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
4985 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
4991 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
4997 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
5003 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
5009 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
5015 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
5017 /* Bit 1 : Pin 1 */
5018 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5021 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
5027 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
5036 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5037 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5043 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5044 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5050 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5051 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5057 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5058 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5064 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5065 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5071 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5072 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5078 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5079 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5085 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5086 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5092 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5093 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5099 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5100 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5106 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5107 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5113 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5114 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5120 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5121 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5127 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5128 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5134 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5135 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5141 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5142 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5148 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5149 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5155 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5156 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5162 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5163 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5169 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5170 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5176 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5177 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5183 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5184 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5190 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5191 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5197 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5198 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5204 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5205 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5211 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5212 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5218 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5219 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5225 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5226 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5232 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5233 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5239 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5240 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5242 /* Bit 1 : Pin 1 */
5243 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5246 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5247 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5253 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5254 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5263 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5264 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5270 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5271 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5277 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5278 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5284 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5285 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5291 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5292 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5298 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
5299 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5305 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
5306 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5312 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
5313 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5319 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
5320 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5326 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
5327 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5333 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
5334 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5340 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
5341 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5347 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
5348 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5354 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
5355 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5361 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
5362 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5368 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
5369 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5375 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
5376 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5382 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
5383 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5389 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
5390 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5396 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
5397 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5403 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
5404 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5410 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
5411 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has…
5417 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
5418 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5424 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
5425 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5431 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
5432 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5438 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
5439 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5445 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
5446 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5452 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
5453 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5459 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
5460 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5466 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
5467 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5469 /* Bit 1 : Pin 1 */
5470 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5473 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
5474 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5480 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
5481 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has …
5490 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
5496 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
5502 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
5508 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
5514 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
5520 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
5526 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
5532 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
5538 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
5544 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
5550 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
5556 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
5562 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
5568 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
5574 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
5580 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
5586 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
5592 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
5598 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
5604 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
5610 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
5616 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
5622 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
5628 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
5634 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
5640 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
5646 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
5652 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
5658 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
5664 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
5666 /* Bit 1 : Pin 1 */
5667 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5670 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
5676 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
5685 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
5691 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
5697 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
5703 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
5709 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
5715 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
5721 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
5727 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
5733 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
5739 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
5745 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
5751 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
5757 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
5763 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
5769 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
5775 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
5781 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
5787 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
5793 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
5799 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
5805 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
5811 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
5817 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
5823 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
5829 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
5835 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
5841 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
5847 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
5853 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
5859 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
5861 /* Bit 1 : Pin 1 */
5862 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5865 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
5871 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
5880 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
5881 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5887 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
5888 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5894 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
5895 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5901 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
5902 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5908 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
5909 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5915 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
5916 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5922 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
5923 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5929 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
5930 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5936 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
5937 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5943 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
5944 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5950 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
5951 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5957 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
5958 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5964 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
5965 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5971 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
5972 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5978 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
5979 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5985 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
5986 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5992 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
5993 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
5999 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
6000 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6006 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
6007 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6013 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
6014 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6020 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
6021 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6027 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
6028 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has…
6034 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
6035 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6041 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
6042 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6048 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
6049 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6055 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
6056 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6062 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
6063 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6069 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
6070 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6076 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
6077 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6083 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
6084 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6086 /* Bit 1 : Set as output pin 1 */
6087 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6090 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
6091 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6097 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
6098 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has …
6107 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
6108 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6114 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
6115 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6121 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
6122 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6128 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
6129 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6135 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
6136 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6142 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
6143 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6149 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
6150 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6156 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
6157 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6163 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
6164 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6170 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
6171 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6177 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
6178 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6184 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
6185 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6191 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
6192 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6198 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
6199 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6205 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
6206 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6212 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
6213 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6219 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
6220 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6226 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
6227 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6233 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
6234 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6240 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
6241 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6247 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
6248 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6254 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
6255 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' ha…
6261 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
6262 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6268 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
6269 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6275 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
6276 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6282 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
6283 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6289 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
6290 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6296 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
6297 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6303 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
6304 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6310 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
6311 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6313 /* Bit 1 : Set as input pin 1 */
6314 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6317 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
6318 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6324 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
6325 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has…
6330 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to …
6334 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
6336 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to …
6340 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
6342 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to …
6346 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
6348 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to …
6352 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
6354 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to …
6358 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
6360 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to …
6364 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
6366 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to …
6370 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
6372 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to …
6376 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
6378 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to …
6382 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
6384 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to …
6388 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
6390 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to …
6394 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
6396 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to …
6400 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
6402 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to …
6406 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
6408 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to …
6412 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
6414 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to …
6418 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
6420 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to …
6424 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
6426 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to …
6430 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
6432 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to …
6436 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
6438 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to …
6442 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
6444 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to …
6448 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
6450 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to …
6454 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
6456 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to …
6460 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
6462 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to cle…
6466 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
6468 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to cle…
6472 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
6474 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to cle…
6478 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
6480 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to cle…
6484 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
6486 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to cle…
6490 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
6492 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to cle…
6496 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
6498 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to cle…
6502 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
6504 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to cle…
6508 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
6510 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to cle…
6511 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6514 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
6516 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to cle…
6520 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
6529 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
6544 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
6545 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
6546 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
6547 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
6548 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or …
6549 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-…
6550 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-an…
6551 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-…
6557 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
6560 /* Bit 1 : Connect or disconnect input buffer */
6561 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
6564 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
6570 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
6583 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
6585 /* Bit 1 : Enable or disable interrupt for STOPPED event */
6586 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6589 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6595 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6600 /* Bit 2 : Write '1' to Enable interrupt for END event */
6604 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6605 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
6607 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
6608 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6611 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6612 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6614 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
6618 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6619 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6624 /* Bit 2 : Write '1' to Disable interrupt for END event */
6628 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6629 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
6631 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
6632 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6635 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6636 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6638 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
6642 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6643 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6652 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
6667 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
6668 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
6671 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
6677 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit eac…
6706 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
6719 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
6746 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
6750 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6751 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
6753 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
6757 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6758 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
6760 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
6764 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6765 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
6770 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
6774 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6775 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
6777 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
6781 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6782 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
6784 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
6788 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6789 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
6798 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
6804 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
6810 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
6816 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
6822 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
6828 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
6830 /* Bit 1 : Reset from watchdog detected */
6831 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
6834 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
6840 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
6849 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
6855 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
6857 /* Bit 1 : RAM block 1 is on or off/powering up */
6858 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
6861 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
6867 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
6875 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
6880 /* Bits 4..1 : Power failure comparator threshold setting */
6881 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
6900 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
6919 /* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
6923 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
6929 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
6931 /* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
6932 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
6935 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
6941 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
6950 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
6956 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
6958 /* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
6959 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
6962 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
6968 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
6977 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
6986 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
6992 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
6994 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
6995 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
6998 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
7004 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
7012 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
7017 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
7019 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
7020 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7022 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
7027 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
7035 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
7040 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
7042 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
7043 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7045 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
7050 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
7063 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
7069 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
7075 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
7081 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
7087 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
7093 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
7099 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
7105 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
7111 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
7117 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
7123 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
7129 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
7135 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
7141 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
7147 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
7153 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
7159 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
7165 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
7171 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
7177 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
7183 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
7189 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
7195 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
7201 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
7207 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
7213 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
7219 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
7225 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
7231 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
7237 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
7239 /* Bit 1 : Enable or disable channel 1 */
7240 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
7243 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
7249 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
7258 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
7259 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
7265 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
7266 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
7272 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
7273 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
7279 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
7280 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
7286 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
7287 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
7293 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
7294 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
7300 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
7301 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
7307 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
7308 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
7314 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
7315 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
7321 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
7322 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
7328 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
7329 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
7335 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
7336 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
7342 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
7343 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
7349 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
7350 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
7356 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
7357 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
7363 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
7364 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
7370 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
7371 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
7377 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
7378 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
7384 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
7385 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
7391 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
7392 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
7398 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
7399 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
7405 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
7406 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
7412 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
7413 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
7419 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
7420 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
7426 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
7427 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
7433 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
7434 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
7440 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
7441 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
7447 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
7448 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
7454 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
7455 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
7461 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
7462 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
7464 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
7465 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
7468 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
7469 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
7475 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
7476 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
7485 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
7486 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
7492 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
7493 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
7499 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
7500 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
7506 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
7507 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
7513 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
7514 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
7520 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
7521 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
7527 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
7528 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
7534 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
7535 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
7541 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
7542 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
7548 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
7549 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
7555 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
7556 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
7562 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
7563 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
7569 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
7570 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
7576 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
7577 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
7583 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
7584 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
7590 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
7591 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
7597 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
7598 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
7604 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
7605 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
7611 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
7612 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
7618 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
7619 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
7625 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
7626 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
7632 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
7633 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
7639 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
7640 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
7646 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
7647 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
7653 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
7654 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
7660 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
7661 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
7667 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
7668 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
7674 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
7675 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
7681 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
7682 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
7688 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
7689 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
7691 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
7692 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
7695 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
7696 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
7702 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
7703 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
7726 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
7732 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
7738 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
7744 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
7750 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
7756 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
7762 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
7768 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
7774 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
7780 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
7786 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
7792 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
7798 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
7804 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
7810 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
7816 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
7822 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
7828 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
7834 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
7840 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
7846 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
7852 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
7858 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
7864 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
7870 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
7876 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
7882 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
7888 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
7894 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
7900 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
7902 /* Bit 1 : Include or exclude channel 1 */
7903 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
7906 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
7912 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
7932 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
7934 /* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
7938 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
7944 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
7946 /* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
7947 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
7950 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
7956 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
7965 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
7971 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
7973 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
7977 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
7983 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
7985 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
7989 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
7995 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
7997 /* Bit 1 : Enable or disable interrupt for STOPPED event */
7998 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8001 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8006 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
8010 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8011 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
8013 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
8017 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8018 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
8020 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
8024 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8025 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
8027 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
8031 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8032 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
8034 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
8038 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8039 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
8041 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
8045 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8046 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
8048 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
8049 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8052 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8053 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8058 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
8062 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8063 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
8065 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
8069 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8070 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
8072 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
8076 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8077 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
8079 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
8083 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8084 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
8086 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
8090 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8091 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
8093 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
8097 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8098 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
8100 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
8101 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8104 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8105 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8114 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8123 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
8138 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */
8139 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
8142 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */
8154 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to inter…
8156 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
8159 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
8160 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word i…
8161 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4t…
8162 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th …
8190 … PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
8209 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
8226 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
8232 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8238 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
8244 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8250 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
8252 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
8253 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
8256 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8262 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
8267 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
8271 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8272 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8274 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
8278 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8279 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
8281 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
8285 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8286 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
8288 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
8289 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
8292 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8293 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
8295 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
8299 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8300 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
8305 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
8309 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8310 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8312 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
8316 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8317 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
8319 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
8323 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8324 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
8326 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
8327 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
8330 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8331 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
8333 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
8337 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8338 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
8347 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8356 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
8365 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
8390 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
8397 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
8420 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
8433 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
8446 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
8459 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
8493 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
8499 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
8505 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
8511 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
8517 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
8523 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
8525 /* Bit 1 : Shortcut between END event and DISABLE task */
8526 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
8529 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
8535 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
8540 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
8544 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8545 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
8547 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
8551 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8552 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
8554 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
8558 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8559 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
8561 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
8565 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8566 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
8568 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
8572 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8573 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
8575 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
8579 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8580 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
8582 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
8586 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8587 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
8589 /* Bit 3 : Write '1' to Enable interrupt for END event */
8593 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8594 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
8596 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
8600 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8601 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
8603 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
8604 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
8607 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8608 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
8610 /* Bit 0 : Write '1' to Enable interrupt for READY event */
8614 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
8615 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
8620 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
8624 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8625 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
8627 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
8631 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8632 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
8634 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
8638 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8639 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
8641 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
8645 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8646 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
8648 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
8652 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8653 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
8655 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
8659 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8660 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
8662 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
8666 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8667 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
8669 /* Bit 3 : Write '1' to Disable interrupt for END event */
8673 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8674 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
8676 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
8680 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8681 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
8683 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
8684 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
8687 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8688 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
8690 /* Bit 0 : Write '1' to Disable interrupt for READY event */
8694 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
8695 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
8704 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
8741 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
8770 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
8771 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
8773 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
8783 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
8789 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
8804 /* Description: Packet configuration register 1 */
8810 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
8816 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
8838 /* Description: Base address 1 */
8840 /* Bits 31..0 : Base address 1 */
8855 /* Bits 15..8 : Address prefix 1. */
8896 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
8902 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
8908 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
8914 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
8920 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
8926 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
8928 /* Bit 1 : Enable or disable reception on logical address 1. */
8929 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
8932 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
8938 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
8947 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The C…
8949 /* Bits 1..0 : CRC length in number of bytes. */
8953 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
8992 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
9004 …ue. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back a…
9056 /* Bit 9 : TxAdd for device address 1 */
9068 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
9074 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
9080 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
9086 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
9092 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
9098 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
9100 /* Bit 1 : Enable or disable device address matching using device address 1 */
9101 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
9104 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
9110 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
9118 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
9119 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
9126 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification f…
9135 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
9148 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9153 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
9157 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9158 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
9163 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
9167 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9168 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
9177 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
9193 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
9197 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9198 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
9200 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
9204 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9205 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
9207 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
9211 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9212 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
9214 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
9218 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9219 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
9221 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
9222 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9225 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9226 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
9228 /* Bit 0 : Write '1' to Enable interrupt for TICK event */
9232 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9233 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
9238 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
9242 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9243 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
9245 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
9249 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9250 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
9252 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
9256 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9257 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
9259 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
9263 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9264 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
9266 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
9267 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9270 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9271 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
9273 /* Bit 0 : Write '1' to Disable interrupt for TICK event */
9277 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9278 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
9287 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
9293 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
9295 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
9299 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
9305 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
9307 /* Bit 1 : Enable or disable event routing for OVRFLW event */
9308 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9311 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
9317 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
9322 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
9326 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9327 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
9329 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
9333 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9334 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
9336 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
9340 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9341 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
9343 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
9347 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9348 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
9350 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
9351 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9354 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9355 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
9357 /* Bit 0 : Write '1' to Enable event routing for TICK event */
9361 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9362 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
9367 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
9371 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9372 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
9374 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
9378 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9379 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
9381 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
9385 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9386 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
9388 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
9392 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9393 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
9395 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
9396 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9399 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9400 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
9402 /* Bit 0 : Write '1' to Disable event routing for TICK event */
9406 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9407 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
9417 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when R…
9441 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
9447 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
9453 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
9459 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
9465 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
9471 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
9477 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
9483 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
9489 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
9495 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
9501 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
9507 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
9509 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
9513 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
9515 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
9519 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
9525 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
9531 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
9537 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9543 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
9549 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
9555 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
9557 /* Bit 1 : Enable or disable interrupt for END event */
9558 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
9561 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
9567 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
9572 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
9576 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9577 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
9579 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
9583 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9584 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
9586 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
9590 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9591 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
9593 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
9597 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9598 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
9600 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
9604 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9605 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
9607 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
9611 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9612 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
9614 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
9618 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9619 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
9621 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
9625 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9626 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
9628 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
9632 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9633 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
9635 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
9639 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9640 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
9642 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
9646 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9647 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
9649 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
9653 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9654 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
9656 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
9660 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9661 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
9663 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
9667 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9668 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
9670 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
9674 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9675 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
9677 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
9681 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9682 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
9684 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
9688 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9689 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9691 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
9695 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9696 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
9698 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
9702 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9703 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
9705 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
9709 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
9710 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
9712 /* Bit 1 : Write '1' to Enable interrupt for END event */
9713 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
9716 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
9717 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
9719 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
9723 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
9724 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
9729 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
9733 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9734 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
9736 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
9740 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9741 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
9743 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
9747 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9748 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
9750 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
9754 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9755 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
9757 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
9761 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9762 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
9764 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
9768 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9769 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
9771 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
9775 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9776 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
9778 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
9782 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9783 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
9785 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
9789 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9790 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
9792 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
9796 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9797 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
9799 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
9803 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9804 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
9806 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
9810 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9811 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
9813 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
9817 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9818 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
9820 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
9824 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9825 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
9827 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
9831 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9832 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
9834 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
9838 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9839 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
9841 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
9845 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9846 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9848 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
9852 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9853 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
9855 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
9859 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9860 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
9862 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
9866 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
9867 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
9869 /* Bit 1 : Write '1' to Disable interrupt for END event */
9870 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
9873 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
9874 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
9876 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
9880 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
9881 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
9890 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
9899 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
9908 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
9925 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
9942 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
9948 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
9954 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
9964 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
9969 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
9970 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
9971 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
9972 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
9973 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
9974 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
9982 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
9986 /* Bits 1..0 : Positive channel resistor control */
9990 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
10012 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
10023 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
10039 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to cont…
10073 /* Bit 2 : Write '1' to Enable interrupt for READY event */
10077 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10078 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
10083 /* Bit 2 : Write '1' to Disable interrupt for READY event */
10087 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10088 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
10097 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
10146 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
10158 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
10160 /* Bit 1 : Serial clock (SCK) phase */
10161 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
10164 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on …
10170 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
10183 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
10188 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */
10192 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
10193 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
10195 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
10199 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10200 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10202 /* Bit 6 : Write '1' to Enable interrupt for END event */
10206 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10207 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
10209 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10213 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10214 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10216 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
10217 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10220 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10221 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
10226 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */
10230 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
10231 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
10233 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
10237 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10238 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10240 /* Bit 6 : Write '1' to Disable interrupt for END event */
10244 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10245 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
10247 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10251 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10252 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10254 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
10255 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10258 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10259 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
10277 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
10290 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
10303 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
10318 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
10351 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10381 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10390 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
10392 /* Bit 1 : Serial clock (SCK) phase */
10393 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
10396 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on…
10402 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
10422 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
10427 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
10431 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10432 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
10434 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10438 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10439 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10441 /* Bit 1 : Write '1' to Enable interrupt for END event */
10442 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
10445 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10446 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
10451 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
10455 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10456 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
10458 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10462 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10463 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10465 /* Bit 1 : Write '1' to Disable interrupt for END event */
10466 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
10469 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10470 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
10475 /* Bits 1..0 : Semaphore status */
10479 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
10486 /* Bit 1 : RX buffer overflow detected, and prevented */
10487 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
10490 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
10491 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
10497 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
10498 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
10516 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
10529 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
10542 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
10555 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
10610 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
10612 /* Bit 1 : Serial clock (SCK) phase */
10613 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
10616 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on…
10622 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
10645 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
10649 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10650 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
10655 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
10659 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10660 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
10670 /* Description: Slope of 1st piece wise linear function */
10672 /* Bits 11..0 : Slope of 1st piece wise linear function */
10712 /* Description: y-intercept of 1st piece wise linear function */
10714 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
10754 /* Description: End point of 1st piece wise linear function */
10756 /* Bits 7..0 : End point of 1st piece wise linear function */
10799 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
10805 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
10811 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
10817 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
10819 /* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
10823 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
10829 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
10835 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10841 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10847 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10853 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10855 /* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
10856 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
10859 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10865 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10870 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
10874 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10875 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
10877 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
10881 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10882 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
10884 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
10888 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10889 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
10891 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
10895 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10896 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
10898 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
10902 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10903 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
10905 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
10909 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10910 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
10915 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
10919 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10920 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
10922 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
10926 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10927 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
10929 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
10933 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10934 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
10936 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
10940 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10941 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
10943 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
10947 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10948 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
10950 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
10954 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10955 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
10960 /* Bits 1..0 : Timer mode */
10964 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
10970 /* Bits 1..0 : Timer bit width */
10974 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
10999 /* Bit 1 : Shortcut between BB event and STOP task */
11000 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
11003 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
11009 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11014 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11018 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11019 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
11021 /* Bit 14 : Write '1' to Enable interrupt for BB event */
11025 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
11026 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
11028 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11032 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11033 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
11035 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
11039 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11040 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
11042 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
11046 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11047 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
11049 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11050 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11053 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11054 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11059 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11063 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11064 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
11066 /* Bit 14 : Write '1' to Disable interrupt for BB event */
11070 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
11071 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
11073 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11077 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11078 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11080 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
11084 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11085 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
11087 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
11091 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11092 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
11094 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11095 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11098 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11099 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11104 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11108 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
11109 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */
11111 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
11112 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
11115 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
11116 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */
11122 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
11123 #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */
11192 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
11198 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
11204 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
11210 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11216 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
11225 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
11231 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
11237 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11243 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11249 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
11255 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11257 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11258 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11261 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11266 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
11270 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11271 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
11273 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
11277 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11278 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
11280 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11284 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11285 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11287 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11291 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11292 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11294 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11298 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11299 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
11301 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11305 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11306 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
11308 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11309 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11312 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11313 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11318 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
11322 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11323 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
11325 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
11329 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11330 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
11332 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11336 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11337 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
11339 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11343 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11344 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
11346 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11350 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11351 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
11353 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11357 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11358 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11360 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11361 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11364 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11365 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11370 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11374 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
11376 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
11377 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
11380 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
11386 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
11404 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
11417 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
11461 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11491 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11511 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11517 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11526 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
11532 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
11538 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11544 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11550 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11552 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11553 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11556 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11561 /* Bit 26 : Write '1' to Enable interrupt for READ event */
11565 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
11566 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
11568 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */
11572 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
11573 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
11575 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11579 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11580 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11582 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11586 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11587 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11589 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11593 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11594 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
11596 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11597 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11600 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11601 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11606 /* Bit 26 : Write '1' to Disable interrupt for READ event */
11610 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
11611 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
11613 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */
11617 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
11618 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
11620 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11624 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11625 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
11627 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11631 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11632 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
11634 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11638 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11639 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11641 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11642 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11645 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11646 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11655 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
11661 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
11667 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
11692 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
11705 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
11763 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
11764 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
11767 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
11773 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
11793 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
11799 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
11804 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
11808 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
11809 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
11811 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11815 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11816 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
11818 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
11822 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11823 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
11825 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
11829 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11830 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
11832 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
11833 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
11836 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
11837 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
11839 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
11843 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
11844 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
11849 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
11853 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
11854 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
11856 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11860 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11861 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11863 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
11867 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11868 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
11870 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
11874 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11875 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
11877 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
11878 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
11881 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
11882 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
11884 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
11888 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
11889 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
11898 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
11904 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
11906 /* Bit 1 : Parity error */
11907 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
11910 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
11916 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
11996 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
12001 /* Bits 3..1 : Parity */
12002 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12011 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
12024 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
12030 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
12039 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
12045 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
12051 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
12057 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
12063 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
12069 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
12075 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
12081 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
12087 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
12089 /* Bit 1 : Enable or disable interrupt for NCTS event */
12090 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12093 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
12099 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
12104 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
12108 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12109 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
12111 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
12115 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12116 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
12118 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
12122 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12123 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
12125 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
12129 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
12130 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
12132 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
12136 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
12137 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
12139 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
12143 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12144 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
12146 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
12150 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12151 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
12153 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
12157 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12158 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12160 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
12164 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12165 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
12167 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
12168 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12171 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
12172 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
12174 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
12178 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
12179 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
12184 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
12188 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12189 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
12191 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
12195 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12196 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
12198 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
12202 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12203 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
12205 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
12209 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
12210 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
12212 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
12216 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
12217 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
12219 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
12223 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12224 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
12226 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
12230 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12231 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
12233 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
12237 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12238 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12240 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
12244 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12245 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
12247 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
12248 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12251 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
12252 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
12254 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
12258 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
12259 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
12268 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
12274 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
12276 /* Bit 1 : Parity error */
12277 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12280 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
12286 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
12304 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
12317 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
12330 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
12343 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
12372 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
12419 /* Bits 3..1 : Parity */
12420 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12429 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
12463 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
12485 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protectio…
12494 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
12498 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12499 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
12504 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
12508 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12509 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
12518 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
12527 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not y…
12533 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not y…
12539 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not y…
12545 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not y…
12551 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not y…
12557 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
12559 /* Bit 1 : Request status for RR[1] register */
12560 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
12562 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are alre…
12563 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not y…
12569 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not y…
12585 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
12591 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
12597 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
12603 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
12609 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
12615 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
12617 /* Bit 1 : Enable or disable RR[1] register */
12618 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
12620 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
12621 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
12627 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
12636 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the deb…
12642 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */