Lines Matching +full:ram +full:- +full:up
3 Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
157 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
173 /* Description: Description cluster[n]: Configure the word-aligned start address of region n to pro…
175 /* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a fl…
206 /* Description: Start generation of key-stream. This operation will stop by itself when completed. …
234 /* Description: Key-stream generation complete */
248 /* Description: Deprecated register - CCM error event */
335 …f LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 …
336 …f LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAX…
376 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generat…
382 /* Description: Length of key-stream generated when MODE.LENGTH = Extended. */
384 /* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be great…
410 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key …
414 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_…
420 …ST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_…
425 … Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domai…
453 /* Bit 8 : This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured…
459 /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */
721 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external sour…
722 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
737 …CE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystal…
772 #define CLOCK_LFRCMODE_STATUS_ULP (1UL) /*!< Ultra-low power mode (ULP) */
778 #define CLOCK_LFRCMODE_MODE_ULP (1UL) /*!< Ultra-low power mode (ULP) */
842 /* Bit 3 : Shortcut between UP event and STOP task */
875 /* Bit 2 : Enable or disable interrupt for UP event */
876 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
877 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
903 /* Bit 2 : Write '1' to enable interrupt for UP event */
904 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
905 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
934 /* Bit 2 : Write '1' to disable interrupt for UP event */
935 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
936 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
961 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */
962 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */
989 /* Description: Reference source select for single-ended mode */
1032 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1038 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1040 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1569 #define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */
1573 /* Description: RAM variant */
1575 /* Bits 31..0 : RAM variant */
1576 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1577 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1578 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
1579 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
1580 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
1581 #define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */
1582 #define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */
1650 /* Description: Y-intercept B0 */
1652 /* Bits 13..0 : B (y-intercept) */
1657 /* Description: Y-intercept B1 */
1659 /* Bits 13..0 : B (y-intercept) */
1664 /* Description: Y-intercept B2 */
1666 /* Bits 13..0 : B (y-intercept) */
1671 /* Description: Y-intercept B3 */
1673 /* Bits 13..0 : B (y-intercept) */
1678 /* Description: Y-intercept B4 */
1680 /* Bits 13..0 : B (y-intercept) */
1685 /* Description: Y-intercept B5 */
1687 /* Bits 13..0 : B (y-intercept) */
2063 /* Description: Inter-IC Sound */
2080 /* Description: The RXD.PTR register has been copied to internal double-buffers.
2095 /* Description: The TDX.PTR register has been copied to internal double-buffers.
2273 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
2274 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2283 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2296 /* Description: Receive buffer RAM start address. */
2298 …ffer Data RAM start address. When receiving, words containing samples will be written to this addr…
2303 /* Description: Transmit buffer RAM start address. */
2305 …er Data RAM start address. When transmitting, words containing samples will be fetched from this a…
2463 /* Bit 3 : Shortcut between UP event and STOP task */
2497 /* Bit 2 : Write '1' to enable interrupt for UP event */
2498 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2499 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
2528 /* Bit 2 : Write '1' to disable interrupt for UP event */
2529 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2530 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
2555 …_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */
2556 …_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */
2915 /* Description: Enable or disable non-maskable interrupt */
2917 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
2923 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
2929 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
2935 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
2941 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
2947 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
2953 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
2959 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
2965 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
2971 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
2977 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
2983 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
2990 /* Description: Enable non-maskable interrupt */
2992 /* Bit 27 : Write '1' to enable non-maskable interrupt for PREGION[1].RA event */
2999 /* Bit 26 : Write '1' to enable non-maskable interrupt for PREGION[1].WA event */
3006 /* Bit 25 : Write '1' to enable non-maskable interrupt for PREGION[0].RA event */
3013 /* Bit 24 : Write '1' to enable non-maskable interrupt for PREGION[0].WA event */
3020 /* Bit 7 : Write '1' to enable non-maskable interrupt for REGION[3].RA event */
3027 /* Bit 6 : Write '1' to enable non-maskable interrupt for REGION[3].WA event */
3034 /* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */
3041 /* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */
3048 /* Bit 3 : Write '1' to enable non-maskable interrupt for REGION[1].RA event */
3055 /* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */
3062 /* Bit 1 : Write '1' to enable non-maskable interrupt for REGION[0].RA event */
3069 /* Bit 0 : Write '1' to enable non-maskable interrupt for REGION[0].WA event */
3077 /* Description: Disable non-maskable interrupt */
3079 /* Bit 27 : Write '1' to disable non-maskable interrupt for PREGION[1].RA event */
3086 /* Bit 26 : Write '1' to disable non-maskable interrupt for PREGION[1].WA event */
3093 /* Bit 25 : Write '1' to disable non-maskable interrupt for PREGION[0].RA event */
3100 /* Bit 24 : Write '1' to disable non-maskable interrupt for PREGION[0].WA event */
3107 /* Bit 7 : Write '1' to disable non-maskable interrupt for REGION[3].RA event */
3114 /* Bit 6 : Write '1' to disable non-maskable interrupt for REGION[3].WA event */
3121 /* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */
3128 /* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */
3135 /* Bit 3 : Write '1' to disable non-maskable interrupt for REGION[1].RA event */
3142 /* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */
3149 /* Bit 1 : Write '1' to disable non-maskable interrupt for REGION[0].RA event */
3156 /* Bit 0 : Write '1' to disable non-maskable interrupt for REGION[0].WA event */
4027 /* Description: NFC-A compatible radio */
4107 /* Description: Marks the end of the last transmitted on-air symbol of a frame */
4121 /* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA ha…
4142 /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
4149 /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffe…
4606 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
4608 ….0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM a…
4613 /* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */
4615 /* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */
4626 …X (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the…
4653 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the…
4748 /* Description: NFC-A SENS_RES auto-response settings */
4780 /* Description: NFC-A SEL_RES auto-response settings */
4812 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
4842 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASE…
4849 /* Description: Register for erasing all non-volatile user memory */
4851 …Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enable…
4858 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASE…
4888 /* Description: I-code cache configuration register. */
4903 /* Description: I-code cache hit counter. */
4910 /* Description: I-code cache miss counter. */
6634 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or …
6635 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-…
6636 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-an…
6637 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-…
6644 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
6691 … specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
6800 …o (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[…
6801 … (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0…
6806 …dule gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) …
6809 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
6819 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
6867 /* Description: RAM address pointer to write samples to with EasyDMA */
6876 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
7033 /* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */
7039 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
7045 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into d…
7051 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signa…
7057 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal f…
7063 /* Bit 3 : Reset from CPU lock-up detected */
7081 /* Bit 0 : Reset from pin-reset detected */
7088 /* Description: Deprecated register - RAM status register */
7090 /* Bit 3 : RAM block 3 is on or off/powering up */
7096 /* Bit 2 : RAM block 2 is on or off/powering up */
7102 /* Bit 1 : RAM block 1 is on or off/powering up */
7108 /* Bit 0 : RAM block 0 is on or off/powering up */
7138 /* Description: Power-fail comparator configuration */
7140 /* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to …
7160 …-fail comparator threshold setting. This setting applies both for normal voltage mode (supply conn…
7226 /* Bit 31 : Keep retention on RAM section S15 when RAM section is off */
7232 /* Bit 30 : Keep retention on RAM section S14 when RAM section is off */
7238 /* Bit 29 : Keep retention on RAM section S13 when RAM section is off */
7244 /* Bit 28 : Keep retention on RAM section S12 when RAM section is off */
7250 /* Bit 27 : Keep retention on RAM section S11 when RAM section is off */
7256 /* Bit 26 : Keep retention on RAM section S10 when RAM section is off */
7262 /* Bit 25 : Keep retention on RAM section S9 when RAM section is off */
7268 /* Bit 24 : Keep retention on RAM section S8 when RAM section is off */
7274 /* Bit 23 : Keep retention on RAM section S7 when RAM section is off */
7280 /* Bit 22 : Keep retention on RAM section S6 when RAM section is off */
7286 /* Bit 21 : Keep retention on RAM section S5 when RAM section is off */
7292 /* Bit 20 : Keep retention on RAM section S4 when RAM section is off */
7298 /* Bit 19 : Keep retention on RAM section S3 when RAM section is off */
7304 /* Bit 18 : Keep retention on RAM section S2 when RAM section is off */
7310 /* Bit 17 : Keep retention on RAM section S1 when RAM section is off */
7316 /* Bit 16 : Keep retention on RAM section S0 when RAM section is off */
7322 /* Bit 15 : Keep RAM section S15 on or off in System ON mode. */
7328 /* Bit 14 : Keep RAM section S14 on or off in System ON mode. */
7334 /* Bit 13 : Keep RAM section S13 on or off in System ON mode. */
7340 /* Bit 12 : Keep RAM section S12 on or off in System ON mode. */
7346 /* Bit 11 : Keep RAM section S11 on or off in System ON mode. */
7352 /* Bit 10 : Keep RAM section S10 on or off in System ON mode. */
7358 /* Bit 9 : Keep RAM section S9 on or off in System ON mode. */
7364 /* Bit 8 : Keep RAM section S8 on or off in System ON mode. */
7370 /* Bit 7 : Keep RAM section S7 on or off in System ON mode. */
7376 /* Bit 6 : Keep RAM section S6 on or off in System ON mode. */
7382 /* Bit 5 : Keep RAM section S5 on or off in System ON mode. */
7388 /* Bit 4 : Keep RAM section S4 on or off in System ON mode. */
7394 /* Bit 3 : Keep RAM section S3 on or off in System ON mode. */
7400 /* Bit 2 : Keep RAM section S2 on or off in System ON mode. */
7406 /* Bit 1 : Keep RAM section S1 on or off in System ON mode. */
7412 /* Bit 0 : Keep RAM section S0 on or off in System ON mode. */
7421 /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
7426 /* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
7431 /* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
7436 /* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
7441 /* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
7446 /* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
7451 /* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
7456 /* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
7461 /* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
7466 /* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
7471 /* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
7476 /* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
7481 /* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
7486 /* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
7491 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7496 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7501 /* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
7506 /* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
7511 /* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
7516 /* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
7521 /* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
7526 /* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
7531 /* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
7536 /* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
7541 /* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
7546 /* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
7551 /* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
7556 /* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
7561 /* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
7566 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
7571 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
7576 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
7584 /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
7589 /* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
7594 /* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
7599 /* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
7604 /* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
7609 /* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
7614 /* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
7619 /* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
7624 /* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
7629 /* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
7634 /* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
7639 /* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
7644 /* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
7649 /* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
7654 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7659 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7664 /* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */
7669 /* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */
7674 /* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */
7679 /* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */
7684 /* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */
7689 /* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */
7694 /* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */
7699 /* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */
7704 /* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */
7709 /* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */
7714 /* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */
7719 /* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */
7724 /* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */
7729 /* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */
7734 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
7739 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
8412 /* Description: Description cluster[n]: Channel n event end-point */
8419 /* Description: Description cluster[n]: Channel n task end-point */
8621 /* Description: Description cluster[n]: Channel n task end-point */
8667 …on collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to…
8881 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
8884 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
8885 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
8888 /* Description: Value up to which the pulse generator counter counts */
8890 …14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODE…
8918 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
8921 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
8922 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word i…
8923 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4t…
8924 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th …
8935 /* Description: Description cluster[n]: Beginning address in RAM of this sequence */
8937 /* Bits 31..0 : Beginning address in RAM of this sequence */
9028 /* Description: Non-null report ready */
9342 /* Description: Start transfer from external flash memory to internal RAM */
9349 /* Description: Start transfer from internal RAM to external flash memory */
9417 /* Bits 31..0 : Word-aligned flash memory source address. */
9422 /* Description: RAM destination address */
9424 /* Bits 31..0 : Word-aligned RAM destination address. */
9438 /* Bits 31..0 : Word-aligned flash destination address. */
9443 /* Description: RAM source address */
9445 /* Bits 31..0 : Word-aligned RAM source address. */
9459 /* Bits 31..0 : Word-aligned start address of block to be erased. */
9591 /* Bit 7 : Enable deep power-down mode (DPM) feature. */
9600 #define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL) /*!< 24-bit addressing. */
9601 #define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL) /*!< 32-bit addressing. */
9633 /* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */
9656 /* Bit 2 : Deep power-down mode (DPM) status of external flash. */
9663 /* Description: Set the duration required to enter/exit deep power-down mode (DPM). */
9704 /* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */
9747 #define QSPI_CINSTRCONF_LENGTH_3B (3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. …
9748 #define QSPI_CINSTRCONF_LENGTH_4B (4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. …
9749 #define QSPI_CINSTRCONF_LENGTH_5B (5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. …
9750 #define QSPI_CINSTRCONF_LENGTH_6B (6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. …
9751 #define QSPI_CINSTRCONF_LENGTH_7B (7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. …
9752 #define QSPI_CINSTRCONF_LENGTH_8B (8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. …
9753 #define QSPI_CINSTRCONF_LENGTH_9B (9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. …
9900 /* Description: RADIO has ramped up and is ready to be started */
9998 /* Description: Wireless medium in idle - clear to send */
10005 /* Description: Wireless medium busy - do not send */
10026 /* Description: RADIO has ramped up and is ready to be started TX path */
10033 /* Description: RADIO has ramped up and is ready to be started RX path */
10563 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
10564 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
10565 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
10566 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
10567 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
10568 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
10569 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */
10574 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (F…
10583 #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */
10601 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
10602 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
10603 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
10604 #define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */
10606 /* Bits 23..22 : Length of code indicator - long range */
10610 /* Bit 20 : Include or exclude S1 field in RAM */
10613 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */
10614 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
10670 /* Description: Prefixes bytes for logical addresses 0-3 */
10689 /* Description: Prefixes bytes for logical addresses 4-7 */
10830 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no e…
10948 /* Bit 0 : Radio ramp-up time */
10951 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware…
10952 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification f…
11373 /* Description: Successive approximation register (SAR) analog-to-digital converter */
11376 /* Description: Starts the SAADC and prepares the result buffer in RAM */
11390 /* Description: Stops the SAADC and terminates all on-going conversions */
11397 /* Description: Starts offset auto-calibration */
11411 /* Description: The SAADC has filled up the result buffer */
11418 …n the configuration, multiple conversions might be needed for a result to be transferred to RAM. */
11425 /* Description: Result ready for transfer to RAM */
11914 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< SAADC is ready. No on-going conversions. */
11969 …SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
11974 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to S…
12009 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
12010 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
12017 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
12018 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
12080 /* Description: Maximum number of 16-bit samples to be written to output RAM buffer */
12082 /* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */
12087 /* Description: Number of 16-bit samples written to output RAM buffer since the previous START task…
12089 /* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task…
12386 /* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL …
12388 /* Bit 1 : Stall status for EasyDMA RAM writes */
12394 /* Bit 0 : Stall status for EasyDMA RAM reads */
12745 /* Bit 0 : TX buffer over-read detected, and prevented */
12900 /* Description: Over-read character */
12902 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer…
13001 /* Description: y-intercept of 1st piece wise linear function */
13003 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
13008 /* Description: y-intercept of 2nd piece wise linear function */
13010 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
13015 /* Description: y-intercept of 3rd piece wise linear function */
13017 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
13022 /* Description: y-intercept of 4th piece wise linear function */
13024 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
13029 /* Description: y-intercept of 5th piece wise linear function */
13031 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
13036 /* Description: y-intercept of 6th piece wise linear function */
13038 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
13110 /* Description: Deprecated register - Shut down timer */
13302 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
13332 /* Description: I2C compatible Two-Wire Interface 0 */
13613 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
14030 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
14256 /* Bit 3 : TX buffer over-read detected, and prevented */
14389 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buf…
14391 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buff…
14793 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
14800 /* Description: Receive buffer is filled up */
15360 /* Bits 7..0 : Configure CPU non-intrusive debug features */
15369 …m of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */
15434 /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */
15441 /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */
15462 /* Description: Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buff…
15476 /* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by …
15483 /* Description: Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buf…
15490 /* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by…
16075 /* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */
16078 #define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */
16079 #define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */
16328 #define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */
16329 #define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */
16416 /* Bit 16 : Zero-length data packet received */
16419 #define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
16420 #define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
16436 /* Description: Control of the USB pull-up */
16438 /* Bit 0 : Control of the USB pull-up on the D+ line */
16441 #define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */
16442 #define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */
16445 /* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE ta…
16447 /* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
16450 #define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing…
16451 #define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
16452 #define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
16626 /* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */
16629 …*!< Software must write this value to exit low power mode and before performing a remote wake-up */
16639 #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data pac…
16644 /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
16665 /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
16686 /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
16707 /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
16905 /*lint --flb "Leave library region" */