Lines Matching +full:high +full:- +full:frequency
3 Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
157 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
173 /* Description: Description cluster[n]: Configure the word-aligned start address of region n to pro…
175 /* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a fl…
206 /* Description: Start generation of key-stream. This operation will stop by itself when completed. …
234 /* Description: Key-stream generation complete */
248 /* Description: Deprecated register - CCM error event */
335 …ective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet pay…
336 …ective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet pay…
376 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generat…
382 /* Description: Length of key-stream generated when MODE.LENGTH = Extended. */
384 /* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be great…
410 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key …
414 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_…
420 …ST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_…
425 … Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domai…
453 /* Bit 8 : This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured…
459 /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */
721 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external sour…
722 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
737 …CE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystal…
772 #define CLOCK_LFRCMODE_STATUS_ULP (1UL) /*!< Ultra-low power mode (ULP) */
778 #define CLOCK_LFRCMODE_MODE_ULP (1UL) /*!< Ultra-low power mode (ULP) */
961 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */
962 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */
989 /* Description: Reference source select for single-ended mode */
1032 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1038 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1040 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1569 #define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */
1650 /* Description: Y-intercept B0 */
1652 /* Bits 13..0 : B (y-intercept) */
1657 /* Description: Y-intercept B1 */
1659 /* Bits 13..0 : B (y-intercept) */
1664 /* Description: Y-intercept B2 */
1666 /* Bits 13..0 : B (y-intercept) */
1671 /* Description: Y-intercept B3 */
1673 /* Bits 13..0 : B (y-intercept) */
1678 /* Description: Y-intercept B4 */
1680 /* Bits 13..0 : B (y-intercept) */
1685 /* Description: Y-intercept B5 */
1687 /* Bits 13..0 : B (y-intercept) */
1870 …ection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
2036 …TE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
2063 /* Description: Inter-IC Sound */
2080 /* Description: The RXD.PTR register has been copied to internal double-buffers.
2095 /* Description: The TDX.PTR register has been copied to internal double-buffers.
2217 /* Description: Master clock generator frequency. */
2219 /* Bits 31..0 : Master clock generator frequency. */
2273 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
2274 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2283 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2555 …_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */
2556 …_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */
2915 /* Description: Enable or disable non-maskable interrupt */
2917 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
2923 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
2929 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
2935 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
2941 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
2947 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
2953 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
2959 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
2965 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
2971 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
2977 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
2983 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
2990 /* Description: Enable non-maskable interrupt */
2992 /* Bit 27 : Write '1' to enable non-maskable interrupt for PREGION[1].RA event */
2999 /* Bit 26 : Write '1' to enable non-maskable interrupt for PREGION[1].WA event */
3006 /* Bit 25 : Write '1' to enable non-maskable interrupt for PREGION[0].RA event */
3013 /* Bit 24 : Write '1' to enable non-maskable interrupt for PREGION[0].WA event */
3020 /* Bit 7 : Write '1' to enable non-maskable interrupt for REGION[3].RA event */
3027 /* Bit 6 : Write '1' to enable non-maskable interrupt for REGION[3].WA event */
3034 /* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */
3041 /* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */
3048 /* Bit 3 : Write '1' to enable non-maskable interrupt for REGION[1].RA event */
3055 /* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */
3062 /* Bit 1 : Write '1' to enable non-maskable interrupt for REGION[0].RA event */
3069 /* Bit 0 : Write '1' to enable non-maskable interrupt for REGION[0].WA event */
3077 /* Description: Disable non-maskable interrupt */
3079 /* Bit 27 : Write '1' to disable non-maskable interrupt for PREGION[1].RA event */
3086 /* Bit 26 : Write '1' to disable non-maskable interrupt for PREGION[1].WA event */
3093 /* Bit 25 : Write '1' to disable non-maskable interrupt for PREGION[0].RA event */
3100 /* Bit 24 : Write '1' to disable non-maskable interrupt for PREGION[0].WA event */
3107 /* Bit 7 : Write '1' to disable non-maskable interrupt for REGION[3].RA event */
3114 /* Bit 6 : Write '1' to disable non-maskable interrupt for REGION[3].WA event */
3121 /* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */
3128 /* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */
3135 /* Bit 3 : Write '1' to disable non-maskable interrupt for REGION[1].RA event */
3142 /* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */
3149 /* Bit 1 : Write '1' to disable non-maskable interrupt for REGION[0].RA event */
3156 /* Bit 0 : Write '1' to disable non-maskable interrupt for REGION[0].WA event */
4027 /* Description: NFC-A compatible radio */
4107 /* Description: Marks the end of the last transmitted on-air symbol of a frame */
4608 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-ali…
4748 /* Description: NFC-A SENS_RES auto-response settings */
4780 /* Description: NFC-A SEL_RES auto-response settings */
4812 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
4842 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASE…
4849 /* Description: Register for erasing all non-volatile user memory */
4851 …Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enable…
4858 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASE…
4888 /* Description: I-code cache configuration register. */
4903 /* Description: I-code cache hit counter. */
4910 /* Description: I-code cache miss counter. */
4927 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
4933 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
4939 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
4945 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
4951 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
4957 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
4963 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
4969 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
4975 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
4981 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
4987 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
4993 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
4999 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
5005 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
5011 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
5017 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
5023 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
5029 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
5035 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
5041 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
5047 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
5053 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
5059 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
5065 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
5071 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
5077 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
5083 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
5089 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
5095 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
5101 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
5107 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
5113 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
5122 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5123 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5129 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5130 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5136 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5137 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5143 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5144 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5150 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5151 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5157 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5158 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5164 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5165 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5171 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5172 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5178 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5179 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5185 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5186 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5192 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5193 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5199 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5200 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5206 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5207 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5213 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5214 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5220 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5221 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5227 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5228 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5234 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5235 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5241 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5242 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5248 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5249 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5255 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5256 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5262 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5263 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5269 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5270 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has …
5276 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5277 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5283 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5284 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5290 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5291 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5297 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5298 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5304 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5305 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5311 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5312 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5318 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5319 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5325 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5326 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5332 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5333 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5339 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5340 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has n…
5349 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5356 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5363 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5370 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5377 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5384 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
5391 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
5398 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
5405 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
5412 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
5419 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
5426 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
5433 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
5440 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
5447 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
5454 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
5461 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
5468 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
5475 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
5482 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
5489 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
5496 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
5503 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
5510 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
5517 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
5524 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
5531 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
5538 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
5545 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
5552 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
5559 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
5566 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
5576 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
5582 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
5588 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
5594 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
5600 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
5606 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
5612 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
5618 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
5624 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
5630 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
5636 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
5642 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
5648 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
5654 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
5660 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
5666 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
5672 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
5678 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
5684 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
5690 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
5696 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
5702 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
5708 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
5714 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
5720 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
5726 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
5732 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
5738 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
5744 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
5750 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
5756 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
5762 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
6624 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
6631 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
6632 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
6633 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
6634 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or …
6635 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-…
6636 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-an…
6637 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-…
6778 /* Bits 31..0 : PDM_CLK frequency */
6806 …dule gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) …
6809 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
6819 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
7063 /* Bit 3 : Reset from CPU lock-up detected */
7081 /* Bit 0 : Reset from pin-reset detected */
7088 /* Description: Deprecated register - RAM status register */
7138 /* Description: Power-fail comparator configuration */
7140 /* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to …
7160 …-fail comparator threshold setting. This setting applies both for normal voltage mode (supply conn…
7221 #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VD…
8412 /* Description: Description cluster[n]: Channel n event end-point */
8419 /* Description: Description cluster[n]: Channel n task end-point */
8621 /* Description: Description cluster[n]: Channel n task end-point */
8881 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
8884 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
8885 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
8921 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
8922 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word i…
8923 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4t…
8924 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th …
9028 /* Description: Non-null report ready */
9192 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
9417 /* Bits 31..0 : Word-aligned flash memory source address. */
9424 /* Bits 31..0 : Word-aligned RAM destination address. */
9438 /* Bits 31..0 : Word-aligned flash destination address. */
9445 /* Bits 31..0 : Word-aligned RAM source address. */
9459 /* Bits 31..0 : Word-aligned start address of block to be erased. */
9591 /* Bit 7 : Enable deep power-down mode (DPM) feature. */
9600 #define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL) /*!< 24-bit addressing. */
9601 #define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL) /*!< 32-bit addressing. */
9623 /* Bits 31..28 : SCK frequency is given as 32 MHz / (SCKFREQ + 1). */
9633 /* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */
9639 /* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. V…
9656 /* Bit 2 : Deep power-down mode (DPM) status of external flash. */
9663 /* Description: Set the duration required to enter/exit deep power-down mode (DPM). */
9704 /* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */
9747 #define QSPI_CINSTRCONF_LENGTH_3B (3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. …
9748 #define QSPI_CINSTRCONF_LENGTH_4B (4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. …
9749 #define QSPI_CINSTRCONF_LENGTH_5B (5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. …
9750 #define QSPI_CINSTRCONF_LENGTH_6B (6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. …
9751 #define QSPI_CINSTRCONF_LENGTH_7B (7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. …
9752 #define QSPI_CINSTRCONF_LENGTH_8B (8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. …
9753 #define QSPI_CINSTRCONF_LENGTH_9B (9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. …
9998 /* Description: Wireless medium in idle - clear to send */
10005 /* Description: Wireless medium busy - do not send */
10537 /* Description: Frequency */
10545 /* Bits 6..0 : Radio channel frequency */
10546 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
10547 …QUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
10563 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
10564 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
10565 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
10566 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
10567 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
10568 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
10569 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */
10574 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (F…
10583 #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */
10601 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
10602 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
10603 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
10604 #define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */
10606 /* Bits 23..22 : Length of code indicator - long range */
10670 /* Description: Prefixes bytes for logical addresses 0-3 */
10689 /* Description: Prefixes bytes for logical addresses 4-7 */
10830 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no e…
10946 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
10948 /* Bit 0 : Radio ramp-up time */
10951 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware…
10952 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification f…
11358 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when R…
11373 /* Description: Successive approximation register (SAR) analog-to-digital converter */
11390 /* Description: Stops the SAADC and terminates all on-going conversions */
11397 /* Description: Starts offset auto-calibration */
11446 /* Description: Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH */
11914 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< SAADC is ready. No on-going conversions. */
11974 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to S…
12009 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
12010 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
12017 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
12018 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
12022 /* Description: Description cluster[n]: High/low limits for event monitoring of a channel */
12024 /* Bits 31..16 : High level limit */
12025 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
12026 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. …
12044 …pling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher…
12080 /* Description: Maximum number of 16-bit samples to be written to output RAM buffer */
12082 /* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */
12087 /* Description: Number of 16-bit samples written to output RAM buffer since the previous START task…
12089 /* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task…
12199 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
12202 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
12203 …CY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
12218 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12478 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
12481 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
12482 …Y_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
12559 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12582 …on between edge of CSN and edge of SCK and minimum duration CSN must stay high between transaction…
12584 …on between edge of CSN and edge of SCK and minimum duration CSN must stay high between transaction…
12594 #define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */
12595 #define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */
12617 …s. The PSEL.DCX line will be low during transmission of command bytes and high during transmission…
12745 /* Bit 0 : TX buffer over-read detected, and prevented */
12877 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
12900 /* Description: Over-read character */
12902 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer…
13001 /* Description: y-intercept of 1st piece wise linear function */
13003 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
13008 /* Description: y-intercept of 2nd piece wise linear function */
13010 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
13015 /* Description: y-intercept of 3rd piece wise linear function */
13017 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
13022 /* Description: y-intercept of 4th piece wise linear function */
13024 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
13029 /* Description: y-intercept of 5th piece wise linear function */
13031 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
13036 /* Description: y-intercept of 6th piece wise linear function */
13038 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
13110 /* Description: Deprecated register - Shut down timer */
13302 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
13332 /* Description: I2C compatible Two-Wire Interface 0 */
13595 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
13597 /* Bits 31..0 : TWI master clock frequency */
13598 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
13599 …CY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
13613 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
13952 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
13954 /* Bits 31..0 : TWI master clock frequency */
13955 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
13956 …Y_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
14030 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
14256 /* Bit 3 : TX buffer over-read detected, and prevented */
14389 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buf…
14391 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buff…
14442 /* Description: CTS is deactivated (set high). Not Clear To Send. */
14786 /* Description: CTS is deactivated (set high). Not Clear To Send. */
15360 /* Bits 7..0 : Configure CPU non-intrusive debug features */
15367 /* Description: GPIO reference voltage / external output supply voltage in high voltage mode */
15369 …m of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */
15434 /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */
15441 /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */
16328 #define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */
16329 #define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */
16416 /* Bit 16 : Zero-length data packet received */
16419 #define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
16420 #define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
16436 /* Description: Control of the USB pull-up */
16438 /* Bit 0 : Control of the USB pull-up on the D+ line */
16441 #define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */
16442 #define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */
16445 /* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE ta…
16447 /* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */
16450 #define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing…
16451 #define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
16452 #define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
16626 /* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */
16629 …*!< Software must write this value to exit low power mode and before performing a remote wake-up */
16639 #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data pac…
16905 /*lint --flb "Leave library region" */