Lines Matching full:enabled

83 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
90 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
97 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
107 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
114 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
121 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
270 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
277 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
284 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
294 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
301 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
308 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
567 #define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
574 #define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
581 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
588 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
595 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
602 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
612 #define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
619 #define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
626 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
633 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
640 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
647 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
900 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
907 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
914 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
921 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
931 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
938 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
945 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
952 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1049 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1062 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */
1103 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1110 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1120 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1127 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1261 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1268 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1275 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1282 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1289 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1296 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1303 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1310 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1317 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1324 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1331 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1338 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1345 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1352 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1359 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1366 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1376 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1383 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1390 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1397 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1404 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1411 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1418 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1425 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1432 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1439 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1446 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1453 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1460 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1467 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1474 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1481 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1891 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1904 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1911 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1918 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1925 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1932 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1939 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1946 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1953 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1960 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1970 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1977 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1984 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1991 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1998 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2005 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2012 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2019 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2026 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2066 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */
2081 …When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAX…
2096 …When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAX…
2130 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2137 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2144 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2154 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2161 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2168 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2196 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
2205 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2494 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2501 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2508 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2515 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2525 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2532 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2539 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2546 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2631 #define LPCOMP_HYST_HYST_Enabled (1UL) /*!< Comparator hysteresis enabled */
2747 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2754 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2761 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2768 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2775 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2782 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2789 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2796 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2803 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2810 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2817 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2824 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2834 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2841 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2848 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2855 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2862 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2869 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2876 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2883 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2890 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2897 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2904 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2911 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2996 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3003 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3010 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3017 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3024 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3031 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3038 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3045 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3052 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3059 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3066 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3073 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3083 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3090 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3097 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3104 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3111 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3118 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3125 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3132 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3139 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3146 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3153 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3160 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3164 …errupt in region n, write access detected while corresponding subregion was enabled for watching */
3359 …terrupt in region n, read access detected while corresponding subregion was enabled for watching */
3635 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3642 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3649 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3656 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3663 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3670 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3677 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3684 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3691 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3698 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3705 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3712 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3722 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3729 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3736 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3743 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3750 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3757 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3764 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3771 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3778 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3785 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3792 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3799 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
4304 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4311 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4318 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4325 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4332 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4339 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4346 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4353 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4360 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4367 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4374 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4381 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4388 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4395 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4402 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4412 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4419 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4426 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4433 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4440 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4447 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4454 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4461 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4468 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4475 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4482 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4489 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4496 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4503 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4510 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4739 … collision resolution function. This setting must be done before the NFCT peripheral is enabled. */
4744 #define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */
4831 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
4832 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
4851 …on-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN …
4867 …ll user information configuration registers. Note that the erase must be enabled using CONFIG.WEN …
6725 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6732 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6739 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6749 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6756 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6763 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6947 #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
6954 #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
6961 #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
6968 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6975 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6982 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6992 #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
6999 #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
7006 #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
7013 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
7020 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
7027 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
7964 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
7971 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
7978 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
7985 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
7992 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
7999 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
8006 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
8013 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
8020 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
8027 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
8034 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
8041 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
8048 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
8055 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
8062 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
8069 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
8076 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
8083 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
8090 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
8097 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
8104 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
8111 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
8118 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
8125 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
8132 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
8139 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
8146 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
8153 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
8160 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
8167 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
8174 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
8181 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
8191 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
8198 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
8205 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
8212 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
8219 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
8226 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
8233 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
8240 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
8247 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
8254 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
8261 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
8268 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
8275 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
8282 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
8289 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
8296 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
8303 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
8310 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
8317 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
8324 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
8331 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
8338 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
8345 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
8352 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
8359 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
8366 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
8373 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
8380 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
8387 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
8394 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
8401 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
8408 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
8639 /* Description: Description collection[n]: Loads the first PWM value on all enabled channels from s…
8646 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=…
8772 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8779 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8786 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8793 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8800 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8807 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8814 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8824 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8831 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8838 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8845 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8852 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8859 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8866 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9107 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9114 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9121 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9128 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9135 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9145 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9152 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
9159 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
9166 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
9173 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
9307 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
9392 #define QSPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
9402 #define QSPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
9716 /* Bit 16 : Enable long frame mode. When enabled, a custom instruction transaction has to be ended …
9720 #define QSPI_CINSTRCONF_LFEN_Enable (1UL) /*!< Long frame mode enabled */
10177 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */
10184 #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
10191 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
10198 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
10205 #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
10212 #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
10219 #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
10226 #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
10233 #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10240 #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
10247 #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
10254 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
10261 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
10268 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
10275 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
10282 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
10289 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
10296 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
10303 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10310 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
10317 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
10324 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10334 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */
10341 #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
10348 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
10355 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
10362 #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
10369 #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
10376 #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
10383 #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
10390 #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10397 #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
10404 #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
10411 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
10418 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
10425 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
10432 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
10439 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
10446 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
10453 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
10460 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10467 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
10474 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
10481 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10779 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
10780 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
10781 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled …
10894 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
10900 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
10906 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
10912 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
10918 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
10924 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
10930 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
10936 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
10978 …rances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
11049 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
11059 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
11069 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
11138 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11145 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11152 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11159 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11166 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11173 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11183 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11190 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11197 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11204 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11211 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11218 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11267 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11274 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11281 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11288 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11295 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11302 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
11312 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
11319 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
11326 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
11333 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
11340 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
11347 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
11601 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11608 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11615 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11622 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11629 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11636 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11643 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11650 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11657 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
11664 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
11671 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
11678 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
11685 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
11692 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
11699 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
11706 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
11713 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11720 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
11727 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
11734 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
11741 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
11748 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
11758 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
11765 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
11772 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
11779 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
11786 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
11793 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
11800 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
11807 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
11814 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
11821 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
11828 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
11835 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
11842 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
11849 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
11856 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
11863 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
11870 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11877 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
11884 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
11891 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
11898 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
11905 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
11969 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
12111 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
12121 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
12316 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
12323 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12330 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12337 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12344 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12354 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
12361 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12368 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12375 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12382 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
12683 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
12690 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12697 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
12707 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
12714 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12721 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
12938 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
12948 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
13212 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
13219 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
13226 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
13233 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
13240 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
13247 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
13257 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
13264 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
13271 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
13278 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
13285 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
13292 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
13433 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13440 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
13447 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13454 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
13461 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
13468 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13478 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13485 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
13492 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13499 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
13506 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
13513 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13790 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
13797 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
13804 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13811 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13818 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13825 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
13832 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
13842 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
13849 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
13856 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13863 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
13870 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
13877 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
13884 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14170 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
14177 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
14184 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14191 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14198 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14205 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14215 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
14222 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
14229 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14236 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14243 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14250 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
14380 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
14386 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
14498 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
14505 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14512 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14519 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
14526 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
14533 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
14543 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
14550 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
14557 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14564 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
14571 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
14578 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
14737 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
14946 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
14953 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14960 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
14967 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
14974 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
14981 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
14988 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
14995 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
15002 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15009 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
15016 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
15026 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
15033 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15040 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
15047 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
15054 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
15061 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
15068 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
15075 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
15082 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
15089 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
15096 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
15289 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
15717 #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */
15724 #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
15731 #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
15738 #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
15745 #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
15752 #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
15759 #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
15766 #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
15773 #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
15780 #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
15787 #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
15794 #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
15801 #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
15808 #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
15815 #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
15822 #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
15829 #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
15836 #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
15843 #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
15850 #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
15857 #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
15864 #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
15871 #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
15878 #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
15885 #define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */
15895 #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */
15902 #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
15909 #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
15916 #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
15923 #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
15930 #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
15937 #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
15944 #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
15951 #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
15958 #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
15965 #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
15972 #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
15979 #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
15986 #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
15993 #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
16000 #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
16007 #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
16014 #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
16021 #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
16028 #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
16035 #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
16042 #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
16049 #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
16056 #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
16063 #define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */
16433 #define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */
16750 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
16760 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
16778 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are alre…
16779 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not y…
16784 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are alre…
16785 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not y…
16790 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are alre…
16791 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not y…
16796 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are alre…
16797 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not y…
16802 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are alre…
16803 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not y…
16808 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are alre…
16809 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
16814 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are alre…
16815 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not y…
16820 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are alre…
16821 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not y…