Lines Matching full:enabled

83 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
90 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
97 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
107 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
114 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
121 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
179 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enabled */
185 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enabled */
191 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enabled */
197 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enabled */
203 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enabled */
209 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enabled */
215 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enabled */
221 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enabled */
227 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enabled */
233 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enabled */
239 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enabled */
245 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enabled */
251 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enabled */
257 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enabled */
263 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enabled */
269 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enabled */
275 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enabled */
281 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enabled */
287 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enabled */
293 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enabled */
299 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enabled */
305 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enabled */
311 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enabled */
317 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enabled */
323 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enabled */
329 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enabled */
335 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enabled */
341 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enabled */
347 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enabled */
353 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enabled */
359 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enabled */
365 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enabled */
374 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
380 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
386 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
392 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
398 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
404 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
410 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
416 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
422 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
428 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
434 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
440 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
446 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
452 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
458 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
464 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
472 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enabled in debug */
544 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
551 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
558 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
568 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
575 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
582 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
761 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
768 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
775 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
782 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
792 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
799 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
806 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
813 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1024 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1031 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1038 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1045 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1055 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1062 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1069 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1076 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1173 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1214 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1221 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1231 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1238 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1372 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1379 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1386 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1393 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1400 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1407 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1414 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1421 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1428 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1435 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1442 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1449 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1456 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1463 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1470 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1477 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1487 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1494 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1501 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1508 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1515 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1522 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1529 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1536 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1543 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1550 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1557 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1564 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1571 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1578 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1585 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1592 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1855 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1868 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1875 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1882 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1889 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1896 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1903 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1910 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1917 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
1924 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
1934 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
1941 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
1948 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
1955 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
1962 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
1969 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
1976 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
1983 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
1990 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2041 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
2042 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
2061 …on-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN …
2077 …ll user information configuration registers. Note that the erase must be enabled using CONFIG.WEN …
3906 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
3913 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
3920 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
3930 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
3937 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
3944 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4087 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4094 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4101 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4111 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4118 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4125 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4516 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
4523 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
4530 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
4537 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
4544 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
4551 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
4558 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
4565 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
4572 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
4579 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
4586 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
4593 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
4600 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
4607 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
4614 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
4621 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
4628 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
4635 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
4642 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
4649 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
4656 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
4663 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
4670 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
4677 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
4684 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
4691 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
4698 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
4705 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
4712 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
4719 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
4726 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
4733 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
4743 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
4750 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
4757 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
4764 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
4771 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
4778 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
4785 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
4792 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
4799 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
4806 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
4813 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
4820 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
4827 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
4834 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
4841 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
4848 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
4855 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
4862 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
4869 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
4876 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
4883 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
4890 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
4897 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
4904 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
4911 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
4918 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
4925 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
4932 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
4939 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
4946 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
4953 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
4960 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
5191 /* Description: Description collection[n]: Loads the first PWM value on all enabled channels from s…
5198 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=…
5324 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5331 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5338 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5345 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5352 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5359 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5366 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5376 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5383 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5390 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5397 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5404 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5411 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5418 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5655 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5662 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
5669 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
5676 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
5683 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
5693 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5700 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
5707 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
5714 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
5721 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
5843 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
6068 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
6075 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
6082 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
6089 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
6096 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
6103 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
6110 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
6117 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6124 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
6131 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
6138 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
6148 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
6155 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
6162 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
6169 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
6176 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
6183 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
6190 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
6197 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6204 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
6211 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
6218 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
6476 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
6477 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
6478 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled …
6591 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
6597 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
6603 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
6609 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
6615 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
6621 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
6627 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
6633 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
6701 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
6711 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
6721 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
6790 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
6797 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
6804 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
6811 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
6818 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
6825 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
6835 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
6842 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
6849 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
6856 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
6863 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
6870 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
6919 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
6926 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
6933 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
6940 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
6947 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
6954 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
6964 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
6971 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
6978 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
6985 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
6992 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
6999 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
7035 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */
7253 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
7260 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
7267 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
7274 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
7281 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
7288 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
7295 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
7302 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
7309 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
7316 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
7323 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
7330 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
7337 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
7344 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
7351 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
7358 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
7365 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7372 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
7379 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
7386 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
7393 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7400 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
7410 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
7417 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
7424 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
7431 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
7438 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
7445 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
7452 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
7459 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
7466 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
7473 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
7480 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
7487 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
7494 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
7501 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
7508 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
7515 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
7522 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7529 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
7536 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
7543 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
7550 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7557 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7619 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE nu…
7826 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
7833 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7840 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7847 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7854 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7864 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7871 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
7878 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7885 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
7892 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8100 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
8107 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
8114 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8124 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
8131 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
8138 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8339 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
8349 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
8613 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8620 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8627 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8634 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8641 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8648 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8658 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8665 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8672 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
8679 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
8686 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
8693 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
8910 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8917 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
8924 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8931 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8938 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
8945 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
8952 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8962 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
8969 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
8976 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8983 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
8990 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
8997 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9004 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9282 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
9289 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
9296 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9303 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9310 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9317 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9327 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
9334 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
9341 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9348 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9355 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9362 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9484 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
9490 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
9706 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
9713 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9720 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9727 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
9734 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9741 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
9748 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
9755 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
9762 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
9769 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
9776 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
9786 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
9793 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9800 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9807 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
9814 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9821 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
9828 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
9835 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
9842 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
9849 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
9856 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
10033 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
10107 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10117 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
10135 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are alre…
10136 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not y…
10141 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are alre…
10142 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not y…
10147 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are alre…
10148 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not y…
10153 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are alre…
10154 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not y…
10159 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are alre…
10160 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not y…
10165 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are alre…
10166 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not y…
10171 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are alre…
10172 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not y…
10177 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are alre…
10178 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not y…