Lines Matching full:on

26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
44 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
49 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
51 /* Bit 1 : Enable interrupt on RESOLVED event. */
56 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
58 /* Bit 0 : Enable interrupt on END event. */
63 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
68 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
73 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
75 /* Bit 1 : Disable interrupt on RESOLVED event. */
80 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
82 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
87 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
128 /* Bit 0 : Enable interrupt on END event. */
133 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
138 /* Bit 0 : Disable interrupt on END event. */
143 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
242 /* Bit 2 : Enable interrupt on ERROR event. */
247 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
249 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
254 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
256 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
261 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
266 /* Bit 2 : Disable interrupt on ERROR event. */
271 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
273 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
278 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
280 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
285 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
330 /* Bit 4 : Enable interrupt on CTTO event. */
335 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
337 /* Bit 3 : Enable interrupt on DONE event. */
342 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
344 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
349 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
351 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
356 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
361 /* Bit 4 : Disable interrupt on CTTO event. */
366 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
368 /* Bit 3 : Disable interrupt on DONE event. */
373 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
375 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
380 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
382 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
387 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
481 /* Bit 1 : Enable interrupt on ERRORECB event. */
486 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
488 /* Bit 0 : Enable interrupt on ENDECB event. */
493 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
498 /* Bit 1 : Disable interrupt on ERRORECB event. */
503 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
505 /* Bit 0 : Disable interrupt on ENDECB event. */
510 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
2073 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
2074 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
2092 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
2093 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
2114 /* Bit 31 : Enable interrupt on PORT event. */
2119 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
2121 /* Bit 3 : Enable interrupt on IN[3] event. */
2126 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
2128 /* Bit 2 : Enable interrupt on IN[2] event. */
2133 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
2135 /* Bit 1 : Enable interrupt on IN[1] event. */
2140 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
2142 /* Bit 0 : Enable interrupt on IN[0] event. */
2147 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
2152 /* Bit 31 : Disable interrupt on PORT event. */
2157 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
2159 /* Bit 3 : Disable interrupt on IN[3] event. */
2164 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
2166 /* Bit 2 : Disable interrupt on IN[2] event. */
2171 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
2173 /* Bit 1 : Disable interrupt on IN[1] event. */
2178 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
2180 /* Bit 0 : Disable interrupt on IN[0] event. */
2185 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
2196 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
2264 /* Bit 3 : Enable interrupt on CROSS event. */
2269 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
2271 /* Bit 2 : Enable interrupt on UP event. */
2276 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
2278 /* Bit 1 : Enable interrupt on DOWN event. */
2283 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
2285 /* Bit 0 : Enable interrupt on READY event. */
2290 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
2295 /* Bit 3 : Disable interrupt on CROSS event. */
2300 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
2302 /* Bit 2 : Disable interrupt on UP event. */
2307 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
2309 /* Bit 1 : Disable interrupt on DOWN event. */
2314 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
2316 /* Bit 0 : Disable interrupt on READY event. */
2321 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
2386 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and…
2387 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
2388 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
2540 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
2547 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
2554 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
2561 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
2568 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
2575 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
2582 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
2589 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
2596 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
2603 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
2610 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
2617 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
2624 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
2631 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
2638 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
2645 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
2652 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
2659 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
2666 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
2673 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
2680 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
2687 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
2694 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
2701 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
2708 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
2715 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
2722 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
2729 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
2736 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
2743 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
2750 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
2757 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
2767 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
2774 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
2781 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
2788 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
2795 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
2802 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
2809 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
2816 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
2823 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
2830 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
2837 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
2844 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
2851 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
2858 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
2865 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
2872 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
2879 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
2886 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
2893 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
2900 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
2907 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
2914 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
2921 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
2928 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
2935 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
2942 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
2949 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
2956 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
2963 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
2970 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
2977 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
2984 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
3013 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
3051 /* Bit 2 : Enable interrupt on POFWARN event. */
3056 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
3061 /* Bit 2 : Disable interrupt on POFWARN event. */
3066 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
3120 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
3126 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
3132 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
3138 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
3173 /* Description: Ram on/off. */
3179 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
3185 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
3187 /* Bit 1 : RAM block 1 behaviour in ON mode. */
3190 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
3191 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
3193 /* Bit 0 : RAM block 0 behaviour in ON mode. */
3196 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
3197 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
3209 /* Description: Ram on/off. */
3215 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
3221 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
3223 /* Bit 1 : RAM block 3 behaviour in ON mode. */
3226 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
3227 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
3229 /* Bit 0 : RAM block 2 behaviour in ON mode. */
3232 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
3233 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
3247 /* Bit 1 : DCDC power-up force on. */
3442 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
3449 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
3456 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
3463 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
3470 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
3477 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
3484 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
3491 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
3498 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
3505 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
3512 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
3519 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
3526 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
3533 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
3540 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
3547 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
3554 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
3561 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
3568 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
3575 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
3582 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
3589 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
3596 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
3603 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
3610 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
3617 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
3624 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
3631 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
3641 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
3648 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
3655 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
3662 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
3669 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
3676 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
3683 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
3690 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
3697 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
3704 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
3711 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
3718 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
3725 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
3732 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
3739 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
3746 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
3753 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
3760 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
3767 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
3774 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
3781 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
3788 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
3795 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
3802 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
3809 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
3816 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
3823 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
3830 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
4025 /* Bit 2 : Enable interrupt on ACCOF event. */
4030 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
4032 /* Bit 1 : Enable interrupt on REPORTRDY event. */
4037 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
4039 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
4044 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
4049 /* Bit 2 : Disable interrupt on ACCOF event. */
4054 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
4056 /* Bit 1 : Disable interrupt on REPORTRDY event. */
4061 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
4063 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
4068 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
4135 /* Description: Time LED is switched ON before the sample. */
4137 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
4222 /* Bit 10 : Enable interrupt on BCMATCH event. */
4227 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
4229 /* Bit 7 : Enable interrupt on RSSIEND event. */
4234 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
4236 /* Bit 6 : Enable interrupt on DEVMISS event. */
4241 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
4243 /* Bit 5 : Enable interrupt on DEVMATCH event. */
4248 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
4250 /* Bit 4 : Enable interrupt on DISABLED event. */
4255 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
4257 /* Bit 3 : Enable interrupt on END event. */
4262 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
4264 /* Bit 2 : Enable interrupt on PAYLOAD event. */
4269 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
4271 /* Bit 1 : Enable interrupt on ADDRESS event. */
4276 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
4278 /* Bit 0 : Enable interrupt on READY event. */
4283 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
4288 /* Bit 10 : Disable interrupt on BCMATCH event. */
4293 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
4295 /* Bit 7 : Disable interrupt on RSSIEND event. */
4300 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
4302 /* Bit 6 : Disable interrupt on DEVMISS event. */
4307 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
4309 /* Bit 5 : Disable interrupt on DEVMATCH event. */
4314 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
4316 /* Bit 4 : Disable interrupt on DISABLED event. */
4321 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
4323 /* Bit 3 : Disable interrupt on END event. */
4328 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
4330 /* Bit 2 : Disable interrupt on PAYLOAD event. */
4335 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
4337 /* Bit 1 : Disable interrupt on ADDRESS event. */
4342 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
4344 /* Bit 0 : Disable interrupt on READY event. */
4349 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
4438 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
4441 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
4442 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
4504 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
4510 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
4516 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
4522 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
4528 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
4534 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
4540 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
4546 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
4791 /* Bit 0 : Enable interrupt on VALRDY event. */
4796 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
4801 /* Bit 0 : Disable interrupt on VALRDY event. */
4806 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
4840 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
4845 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
4847 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
4852 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
4854 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
4859 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
4861 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
4866 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
4868 /* Bit 1 : Enable interrupt on OVRFLW event. */
4873 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
4875 /* Bit 0 : Enable interrupt on TICK event. */
4880 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
4885 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
4890 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
4892 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
4897 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
4899 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
4904 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
4906 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
4911 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
4913 /* Bit 1 : Disable interrupt on OVRFLW event. */
4918 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
4920 /* Bit 0 : Disable interrupt on TICK event. */
4925 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
4974 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
4981 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
4988 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
4995 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
5002 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
5009 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
5019 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
5026 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
5033 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
5040 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
5047 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
5054 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
5093 /* Bit 2 : Enable interrupt on READY event. */
5098 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
5103 /* Bit 2 : Disable interrupt on READY event. */
5108 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
5159 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data o…
5160 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data…
5193 /* Bit 10 : Enable interrupt on ACQUIRED event. */
5198 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
5200 /* Bit 4 : enable interrupt on ENDRX event. */
5205 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
5207 /* Bit 1 : Enable interrupt on END event. */
5212 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
5217 /* Bit 10 : Disable interrupt on ACQUIRED event. */
5222 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
5224 /* Bit 4 : Disable interrupt on ENDRX event. */
5229 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
5231 /* Bit 1 : Disable interrupt on END event. */
5236 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
5257 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
5264 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
5315 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data …
5316 …define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial dat…
5354 /* Bit 0 : Enable interrupt on DATARDY event. */
5359 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
5364 /* Bit 0 : Disable interrupt on DATARDY event. */
5369 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
5438 /* Bit 19 : Enable interrupt on COMPARE[3] */
5443 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
5445 /* Bit 18 : Enable interrupt on COMPARE[2] */
5450 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
5452 /* Bit 17 : Enable interrupt on COMPARE[1] */
5457 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
5459 /* Bit 16 : Enable interrupt on COMPARE[0] */
5464 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
5469 /* Bit 19 : Disable interrupt on COMPARE[3] */
5474 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
5476 /* Bit 18 : Disable interrupt on COMPARE[2] */
5481 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
5483 /* Bit 17 : Disable interrupt on COMPARE[1] */
5488 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
5490 /* Bit 16 : Disable interrupt on COMPARE[0] */
5495 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
5555 /* Bit 18 : Enable interrupt on SUSPENDED event. */
5560 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
5562 /* Bit 14 : Enable interrupt on BB event. */
5567 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
5569 /* Bit 9 : Enable interrupt on ERROR event. */
5574 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
5576 /* Bit 7 : Enable interrupt on TXDSENT event. */
5581 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
5583 /* Bit 2 : Enable interrupt on READY event. */
5588 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
5590 /* Bit 1 : Enable interrupt on STOPPED event. */
5595 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
5600 /* Bit 18 : Disable interrupt on SUSPENDED event. */
5605 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
5607 /* Bit 14 : Disable interrupt on BB event. */
5612 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
5614 /* Bit 9 : Disable interrupt on ERROR event. */
5619 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
5621 /* Bit 7 : Disable interrupt on TXDSENT event. */
5626 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
5628 /* Bit 2 : Disable interrupt on RXDREADY event. */
5633 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
5635 /* Bit 1 : Disable interrupt on STOPPED event. */
5640 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
5650 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
5657 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
5664 #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
5737 /* Bit 17 : Enable interrupt on RXTO event. */
5742 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
5744 /* Bit 9 : Enable interrupt on ERROR event. */
5749 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
5751 /* Bit 7 : Enable interrupt on TXRDY event. */
5756 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
5758 /* Bit 2 : Enable interrupt on RXRDY event. */
5763 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
5765 /* Bit 1 : Enable interrupt on NCTS event. */
5770 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
5772 /* Bit 0 : Enable interrupt on CTS event. */
5777 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
5782 /* Bit 17 : Disable interrupt on RXTO event. */
5787 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
5789 /* Bit 9 : Disable interrupt on ERROR event. */
5794 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
5796 /* Bit 7 : Disable interrupt on TXRDY event. */
5801 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
5803 /* Bit 2 : Disable interrupt on RXRDY event. */
5808 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
5810 /* Bit 1 : Disable interrupt on NCTS event. */
5815 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
5817 /* Bit 0 : Disable interrupt on CTS event. */
5822 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
5832 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
5834 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character …
5839 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
5846 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
5853 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
5865 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the charact…
5940 …eadback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
5969 /* Bit 0 : Enable interrupt on TIMEOUT event. */
5974 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
5979 /* Bit 0 : Disable interrupt on TIMEOUT event. */
5984 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */