Lines Matching full:enabled

48 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
55 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
62 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
72 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
79 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
86 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
119 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
132 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
142 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
161 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected …
224 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
237 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
246 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
253 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
260 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
270 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
277 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
284 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
303 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
321 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
334 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
341 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
348 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
355 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
365 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
372 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
379 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
386 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
485 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
492 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
502 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
509 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
519 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
2118 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
2125 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
2132 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
2139 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
2146 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
2156 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
2163 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
2170 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
2177 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
2184 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
2222 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
2235 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
2241 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
2247 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
2253 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
2259 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
2268 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
2275 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
2282 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
2289 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
2299 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
2306 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
2313 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
2320 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
2397 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
2539 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
2546 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
2553 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
2560 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
2567 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
2574 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
2581 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
2588 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
2595 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
2602 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
2609 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
2616 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
2623 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
2630 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
2637 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
2644 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
2651 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
2658 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
2665 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
2672 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
2679 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
2686 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
2693 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
2700 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
2707 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
2714 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
2721 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
2728 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
2735 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
2742 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
2749 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
2756 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
2766 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
2773 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
2780 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
2787 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
2794 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
2801 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
2808 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
2815 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
2822 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
2829 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
2836 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
2843 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
2850 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
2857 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
2864 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
2871 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
2878 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
2885 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
2892 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
2899 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
2906 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
2913 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
2920 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
2927 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
2934 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
2941 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
2948 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
2955 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
2962 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
2969 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
2976 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
2983 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
2992 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
3023 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
3024 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
3055 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
3065 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
3163 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
3206 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
3242 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
3270 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
3276 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
3282 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
3288 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
3294 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
3300 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
3306 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
3312 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
3318 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
3324 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
3330 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
3336 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
3342 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
3348 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
3354 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
3360 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
3366 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
3372 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
3378 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
3384 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
3390 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
3396 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
3402 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
3408 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
3414 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
3420 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
3426 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
3432 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
3441 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
3448 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
3455 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
3462 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
3469 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
3476 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
3483 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
3490 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
3497 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
3504 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
3511 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
3518 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
3525 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
3532 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
3539 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
3546 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
3553 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
3560 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
3567 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
3574 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
3581 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
3588 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
3595 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
3602 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
3609 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
3616 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
3623 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
3630 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
3640 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
3647 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
3654 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
3661 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
3668 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
3675 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
3682 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
3689 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
3696 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
3703 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
3710 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
3717 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
3724 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
3731 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
3738 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
3745 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
3752 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
3759 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
3766 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
3773 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
3780 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
3787 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
3794 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
3801 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
3808 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
3815 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
3822 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
3829 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
4014 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
4020 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
4029 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
4036 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
4043 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
4053 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
4060 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
4067 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
4132 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
4162 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
4175 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
4181 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
4187 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
4193 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
4199 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
4205 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
4211 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
4217 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
4226 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
4233 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
4240 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
4247 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
4254 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
4261 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
4268 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
4275 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
4282 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
4292 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
4299 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
4306 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
4313 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
4320 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
4327 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
4334 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
4341 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
4348 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
4436 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
4508 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
4514 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
4520 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
4526 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
4532 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
4538 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
4544 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
4550 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
4590 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
4596 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
4681 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
4687 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
4693 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
4699 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
4705 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
4711 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
4717 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
4723 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
4760 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
4773 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
4786 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
4795 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
4805 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
4815 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
4831 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
4844 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
4851 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
4858 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
4865 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
4872 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
4879 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
4889 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
4896 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
4903 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
4910 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
4917 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
4924 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
4934 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
4940 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
4946 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
4952 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
4958 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
4964 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
4973 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
4980 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
4987 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
4994 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
5001 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
5008 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
5018 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
5025 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
5032 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
5039 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
5046 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
5053 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
5084 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
5097 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
5107 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
5175 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
5188 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
5197 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
5204 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
5211 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
5221 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
5228 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
5235 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
5345 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
5358 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
5368 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
5378 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
5391 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
5397 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
5403 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
5409 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
5415 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
5421 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
5427 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
5433 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
5442 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
5449 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
5456 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
5463 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
5473 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
5480 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
5487 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
5494 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
5531 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
5544 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
5550 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
5559 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
5566 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
5573 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
5580 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
5587 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
5594 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
5604 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
5611 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
5618 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
5625 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
5632 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
5639 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
5673 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
5713 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
5726 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
5732 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
5741 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
5748 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
5755 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
5762 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
5769 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
5776 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
5786 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
5793 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
5800 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
5807 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
5814 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
5821 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
5841 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
5862 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
5916 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
5925 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
5937 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
5943 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
5973 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
5983 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
6001 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has alrea…
6002 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not je…
6007 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has alrea…
6008 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not je…
6013 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has alrea…
6014 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not je…
6019 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has alrea…
6020 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not je…
6025 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has alrea…
6026 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not je…
6031 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has alrea…
6032 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not je…
6037 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has alrea…
6038 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not je…
6043 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has alrea…
6044 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not je…
6053 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
6059 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
6065 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
6071 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
6077 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
6083 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
6089 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
6095 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
6127 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */