2  * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
60  *        switched from low to high after this number of bytes is transmitted
77     /*lint -save -e30*/
82     /*lint -restore*/
90     /*lint -save -e30*/
96     /*lint -restore*/
152     NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
153     NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
173     NRF_SPIM_CSN_POL_LOW  = SPIM_CSNPOL_CSNPOL_LOW, ///< Active low (idle state high).
174     NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL_HIGH ///< Active high (idle state low).
397  * bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1.
459  * @param[in] frequency SPI frequency.
462                                             nrf_spim_frequency_t frequency);
498  * @brief Function for setting the over-read character.
501  * @param[in] orc    Over-read character that is clocked out in case of
502  *                   an over-read of the TXD buffer.
574     p_reg->SHORTS |= spim_shorts_mask;  in nrf_spim_shorts_enable()
580     p_reg->SHORTS &= ~(spim_shorts_mask);  in nrf_spim_shorts_disable()
585     return p_reg->SHORTS;  in nrf_spim_shorts_get()
591     p_reg->INTENSET = spim_int_mask;  in nrf_spim_int_enable()
597     p_reg->INTENCLR = spim_int_mask;  in nrf_spim_int_disable()
603     return (bool)(p_reg->INTENSET & spim_int);  in nrf_spim_int_enable_check()
638     p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);  in nrf_spim_enable()
643     p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);  in nrf_spim_disable()
651     p_reg->PSEL.SCK  = sck_pin;  in nrf_spim_pins_set()
652     p_reg->PSEL.MOSI = mosi_pin;  in nrf_spim_pins_set()
653     p_reg->PSEL.MISO = miso_pin;  in nrf_spim_pins_set()
662     p_reg->PSEL.CSN = pin;  in nrf_spim_csn_configure()
663     p_reg->CSNPOL = polarity;  in nrf_spim_csn_configure()
664     p_reg->IFTIMING.CSNDUR = duration;  in nrf_spim_csn_configure()
672     p_reg->PSELDCX = dcx_pin;  in nrf_spim_dcx_pin_set()
678     p_reg->DCXCNT = dcx_cnt;  in nrf_spim_dcx_cnt_set()
686     p_reg->IFTIMING.RXDELAY = rxdelay;  in nrf_spim_iftiming_set()
693     p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_RX_Msk);  in nrf_spim_stallstat_rx_clear()
698     return (p_reg->STALLSTAT & SPIM_STALLSTAT_RX_Msk) != 0;  in nrf_spim_stallstat_rx_get()
705     p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_TX_Msk);  in nrf_spim_stallstat_tx_clear()
710     return (p_reg->STALLSTAT & SPIM_STALLSTAT_TX_Msk) != 0;  in nrf_spim_stallstat_tx_get()
715                                             nrf_spim_frequency_t frequency)  in nrf_spim_frequency_set()  argument
717     p_reg->FREQUENCY = frequency;  in nrf_spim_frequency_set()
724     p_reg->TXD.PTR    = (uint32_t)p_buffer;  in nrf_spim_tx_buffer_set()
725     p_reg->TXD.MAXCNT = length;  in nrf_spim_tx_buffer_set()
732     p_reg->RXD.PTR    = (uint32_t)p_buffer;  in nrf_spim_rx_buffer_set()
733     p_reg->RXD.MAXCNT = length;  in nrf_spim_rx_buffer_set()
765     p_reg->CONFIG = config;  in nrf_spim_configure()
771     p_reg->ORC = orc;  in nrf_spim_orc_set()
777     p_reg->TXD.LIST = 1;  in nrf_spim_tx_list_enable()
782     p_reg->TXD.LIST = 0;  in nrf_spim_tx_list_disable()
787     p_reg->RXD.LIST = 1;  in nrf_spim_rx_list_enable()
792     p_reg->RXD.LIST = 0;  in nrf_spim_rx_list_disable()