2  * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
66     /*lint -save -e30*/
71     /*lint -restore*/
79     /*lint -save -e30*/
83 …ND[0]),     ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
84 …ND[1]),     ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
87     /*lint -restore*/
121 …NRF_PWM_MODE_UP          = PWM_MODE_UPDOWN_Up,        ///< Up counter (edge-aligned PWM duty cycle…
122 …NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM…
143  * The selected mode determines how the sequence data is read from RAM and
148 …MMON     = PWM_DECODER_LOAD_Common,     ///< 1st half word (16-bit) used in all PWM channels (0-3).
149 …NRF_PWM_LOAD_GROUPED    = PWM_DECODER_LOAD_Grouped,    ///< 1st half word (16-bit) used in channel…
150 …NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel…
151 …NRF_PWM_LOAD_WAVE_FORM  = PWM_DECODER_LOAD_WaveForm    ///< 1st half word (16-bit) used in channel…
222  * in the peripheral's internal register, and the values are loaded from RAM
239 …m_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
246                               *   others (14-0) compose the 15-bit value to be
248     uint16_t length;    ///< Number of 16-bit values in the array pointed by @p values.
254  * @brief Helper macro for calculating the number of 16-bit values in specified
457  * @param[in] top_value  Value up to which the pulse generator counter counts.
524  * @brief Function for setting the mode of loading sequence data from RAM
528  * @param[in] dec_load Mode of loading sequence data from RAM.
539  * This function applies to two-sequence playback (concatenated sequence 0 and 1).
588     p_reg->SHORTS |= pwm_shorts_mask;  in nrf_pwm_shorts_enable()
594     p_reg->SHORTS &= ~(pwm_shorts_mask);  in nrf_pwm_shorts_disable()
600     p_reg->SHORTS = pwm_shorts_mask;  in nrf_pwm_shorts_set()
606     p_reg->INTENSET = pwm_int_mask;  in nrf_pwm_int_enable()
612     p_reg->INTENCLR = pwm_int_mask;  in nrf_pwm_int_disable()
618     p_reg->INTEN = pwm_int_mask;  in nrf_pwm_int_set()
624     return (bool)(p_reg->INTENSET & pwm_int);  in nrf_pwm_int_enable_check()
659     p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);  in nrf_pwm_enable()
664     p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);  in nrf_pwm_disable()
673         p_reg->PSEL.OUT[i] = out_pins[i];  in nrf_pwm_pins_set()
684     p_reg->PRESCALER  = base_clock;  in nrf_pwm_configure()
685     p_reg->MODE       = mode;  in nrf_pwm_configure()
686     p_reg->COUNTERTOP = top_value;  in nrf_pwm_configure()
695     nrf_pwm_seq_ptr_set(      p_reg, seq_id, p_seq->values.p_raw);  in nrf_pwm_sequence_set()
696     nrf_pwm_seq_cnt_set(      p_reg, seq_id, p_seq->length);  in nrf_pwm_sequence_set()
697     nrf_pwm_seq_refresh_set(  p_reg, seq_id, p_seq->repeats);  in nrf_pwm_sequence_set()
698     nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);  in nrf_pwm_sequence_set()
707     p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;  in nrf_pwm_seq_ptr_set()
717     p_reg->SEQ[seq_id].CNT = length;  in nrf_pwm_seq_cnt_set()
726     p_reg->SEQ[seq_id].REFRESH  = refresh;  in nrf_pwm_seq_refresh_set()
735     p_reg->SEQ[seq_id].ENDDELAY = end_delay;  in nrf_pwm_seq_end_delay_set()
742     p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |  in nrf_pwm_decoder_set()
749     p_reg->LOOP = loop_count;  in nrf_pwm_loop_set()